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authorJohn Zhao <john.zhao@intel.com>2021-03-02 09:31:15 -0800
committerPatrick Georgi <pgeorgi@google.com>2021-03-15 06:30:52 +0000
commitf3a8bf13cbfc43e45f0bb6e451608a082b59f7bf (patch)
tree49ed6cbacfc2f3dc43ca075c3a093d8ebea10996 /src
parent80273918d5972157e6576ac983a14244d6074af1 (diff)
downloadcoreboot-f3a8bf13cbfc43e45f0bb6e451608a082b59f7bf.tar.xz
soc/intel/alderlake: Drop 100ms delay and do not poll Link Active
Drop the 100ms delay in the _PS0 method because kernel already adds this 100ms. This change also drops polling TBT PCIe root ports Link Active State because this scheme is not applicable for SW CM. BUG=None TEST=Built Alderlake coreboot image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51191 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/alderlake/acpi/tcss_pcierp.asl14
1 files changed, 0 insertions, 14 deletions
diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
index 3f495be680..07d024a027 100644
--- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
@@ -140,18 +140,6 @@ Method (D3CX, 0, Serialized)
Local1 = L23R
}
STAT = 0x1
-
- /* Wait for LA = 1 */
- Local0 = 0
- Local1 = LASX
- While (Local1 == 0) {
- If (Local0 > 20) {
- Break
- }
- Sleep(5)
- Local0++
- Local1 = LASX
- }
}
/*
@@ -192,8 +180,6 @@ Method (_PS0, 0, Serialized)
If (PMEX == 1) {
PMEX = 0 /* Disable Power Management SCI */
}
-
- Sleep(100) /* Wait for 100ms before return to OS starts any OS activities. */
}
Method (_PS3, 0, Serialized)