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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2021-01-16 14:59:30 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:45:55 +0000 |
| commit | f669c81cf47f91ba66c22db15a6ef911e6e15e50 (patch) | |
| tree | eff7c50fdfeeb1b298d2c368993f258058dea0e9 /src | |
| parent | 4ff66dc08f73a81d181a84a7483489804142a72a (diff) | |
| download | coreboot-f669c81cf47f91ba66c22db15a6ef911e6e15e50.tar.xz | |
northbridge/intel/x4x/dq_dqs.c: Remove repeated word
Change-Id: Iee24c6bf82ab6ff6691707ed0c388cfe492cc925
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/x4x/dq_dqs.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 82dca44f72..4722dfe7a6 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -746,7 +746,7 @@ static enum cb_err increment_to_dqs_edge(struct sysinfo *s, u8 channel, u8 rank) * DDR3 uses flyby topology where the clock signal takes a different path * than the data signal, to allow for better signal intergrity. * Therefore the delay on the data signals needs to account for this. - * This is done by by sampleling the the DQS write (tx) signal back over + * This is done by sampleling the DQS write (tx) signal back over * the DQ signal and looking for delay values where the sample transitions * from high to low. * Here the following is done: |