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authorLee Leahy <leroy.p.leahy@intel.com>2016-05-04 11:59:19 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2016-05-09 17:21:22 +0200
commitf92a98c56e063b34b83a35ac655ea8127d4b546f (patch)
tree64cee51816e7f1daf77ad973fca31fda96f14a3a /src
parent2dfbd93ed6bf830a9655e70d0dd1e26b008cd482 (diff)
downloadcoreboot-f92a98c56e063b34b83a35ac655ea8127d4b546f.tar.xz
coreboot_tables: Extend serial port description
Extend the serial port description to include the input clock frequency and a payload specific value. Without the input frequency it is impossible for the payload to compute the baud-rate divisor without making an assumption about the frequency. This breaks down when the UART is able to support multiple input clock frequencies. Add the UART_PCI_ADDR Kconfig value to specify the unique PCI device being used as the console UART. Specify this value as zero when the UART is not on the PCI bus. Otherwise specify the device using bus, device and function along with setting the valid bit. Currently the only payload to consume these new fields is the EDK-II CorebootPayloadPkg. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Id4b4455bbf9583f0d66c315d38c493a81fd852a8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14609 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/commonlib/include/commonlib/coreboot_tables.h15
-rw-r--r--src/drivers/uart/Kconfig17
-rw-r--r--src/drivers/uart/oxpcie_early.c5
-rw-r--r--src/drivers/uart/pl011.c5
-rw-r--r--src/drivers/uart/uart8250io.c5
-rw-r--r--src/drivers/uart/uart8250mem.c5
-rw-r--r--src/lib/coreboot_table.c2
7 files changed, 54 insertions, 0 deletions
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 5c28791594..7d58fddbb9 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -173,6 +173,21 @@ struct lb_serial {
uint32_t baseaddr;
uint32_t baud;
uint32_t regwidth;
+
+ /* Crystal or input frequency to the chip containing the UART.
+ * Provide the board specific details to allow the payload to
+ * initialize the chip containing the UART and make independent
+ * decisions as to which dividers to select and their values
+ * to eventually arrive at the desired console baud-rate. */
+ uint32_t input_hertz;
+
+ /* UART PCI address: bus, device, function
+ * 1 << 31 - Valid bit, PCI UART in use
+ * Bus << 20
+ * Device << 15
+ * Function << 12
+ */
+ uint32_t uart_pci_addr;
};
#define LB_TAG_CONSOLE 0x0010
diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig
index f4ad011933..ae3e81adb1 100644
--- a/src/drivers/uart/Kconfig
+++ b/src/drivers/uart/Kconfig
@@ -41,3 +41,20 @@ config DRIVERS_UART_PL011
bool
default n
select HAVE_UART_SPECIAL
+
+config UART_USE_REFCLK_AS_INPUT_CLOCK
+ bool
+ default n
+ help
+ Use uart_platform_refclk to specify the input clock value.
+
+config UART_PCI_ADDR
+ hex "UART's PCI bus, device, function address"
+ default 0
+ help
+ Specify zero if the UART is connected to another bus type.
+ For PCI based UARTs, build the value as:
+ * 1 << 31 - Valid bit, PCI UART in use
+ * Bus << 20
+ * Device << 15
+ * Function << 12
diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c
index eb91d31154..6582a9e5ab 100644
--- a/src/drivers/uart/oxpcie_early.c
+++ b/src/drivers/uart/oxpcie_early.c
@@ -92,6 +92,11 @@ void uart_fill_lb(void *data)
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
serial.regwidth = 1;
+ if (IS_ENABLED(CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK))
+ serial.input_hertz = uart_platform_refclk();
+ else
+ serial.input_hertz = 0;
+ serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c
index aa55c682a6..808cb46538 100644
--- a/src/drivers/uart/pl011.c
+++ b/src/drivers/uart/pl011.c
@@ -48,6 +48,11 @@ void uart_fill_lb(void *data)
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
serial.regwidth = 1;
+ if (IS_ENABLED(CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK))
+ serial.input_hertz = uart_platform_refclk();
+ else
+ serial.input_hertz = 0;
+ serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c
index 63bc42fccc..0974005a81 100644
--- a/src/drivers/uart/uart8250io.c
+++ b/src/drivers/uart/uart8250io.c
@@ -139,6 +139,11 @@ void uart_fill_lb(void *data)
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
serial.regwidth = 1;
+ if (IS_ENABLED(CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK))
+ serial.input_hertz = uart_platform_refclk();
+ else
+ serial.input_hertz = 0;
+ serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data);
diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c
index 278ddb8ebb..2f2bd2df56 100644
--- a/src/drivers/uart/uart8250mem.c
+++ b/src/drivers/uart/uart8250mem.c
@@ -156,6 +156,11 @@ void uart_fill_lb(void *data)
serial.regwidth = sizeof(uint32_t);
else
serial.regwidth = sizeof(uint8_t);
+ if (IS_ENABLED(CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK))
+ serial.input_hertz = uart_platform_refclk();
+ else
+ serial.input_hertz = 0;
+ serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 4dbac1930d..3af2be6c9a 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -119,6 +119,8 @@ void lb_add_serial(struct lb_serial *new_serial, void *data)
serial->baseaddr = new_serial->baseaddr;
serial->baud = new_serial->baud;
serial->regwidth = new_serial->regwidth;
+ serial->input_hertz = new_serial->input_hertz;
+ serial->uart_pci_addr = new_serial->uart_pci_addr;
}
void lb_add_console(uint16_t consoletype, void *data)