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| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-21 17:42:52 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-06-27 17:28:53 +0000 |
| commit | fc7bc54e34d496a9fe2d0047eddeb9d1f48de417 (patch) | |
| tree | 7eec64d2ec2e2da5477ad87c5321fc10bdb8cbbf /src | |
| parent | f183626b225d17d1eacfa4b12ffce47e0f4d872d (diff) | |
| download | coreboot-fc7bc54e34d496a9fe2d0047eddeb9d1f48de417.tar.xz | |
sb/intel/common: Add early SPI code
All Intel southbridges with SPI perform this write. Put it inside a
function in common code. Use a different name to avoid a name clash.
As it is only one statement, make it inline so that it can be defined
on the header itself. It is only called once per southbridge anyway.
Change-Id: I3c284d6cffd22949d50b4c4f9846ceaef38d7cda
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/common/early_spi.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/early_spi.h b/src/southbridge/intel/common/early_spi.h new file mode 100644 index 0000000000..ae84f74e83 --- /dev/null +++ b/src/southbridge/intel/common/early_spi.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_EARLY_SPI_H +#define SOUTHBRIDGE_INTEL_COMMON_EARLY_SPI_H + +#include <device/pci_ops.h> + +static inline void enable_spi_prefetching_and_caching(void) +{ + pci_update_config8(PCI_DEV(0, 0x1f, 0), 0xdc, ~(3 << 2), 2 << 2); +} + +#endif |