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authorSubrata Banik <subrata.banik@intel.com>2020-02-20 12:09:45 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-02-25 10:12:19 +0000
commit00b7533629b4b227b182d0edca5ee7275054a03b (patch)
treea73cd6c19b8fa5b989f14f58b809194288d1682d /src
parente5c1aa69c7208fc1c9a0827e971b4b58340da307 (diff)
downloadcoreboot-00b7533629b4b227b182d0edca5ee7275054a03b.tar.xz
soc/intel/common/block: Move smihandler common functions into common code
This patch cleans soc/intel/{apl/cnl/skl/icl/tgl} by moving common soc code into common/block/smihandler.c BUG=b:78109109 TEST=Build and boot KBL/CNL/APL/ICL/TGL platform. Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/smihandler.c12
-rw-r--r--src/soc/intel/cannonlake/smihandler.c43
-rw-r--r--src/soc/intel/common/block/include/intelblocks/smihandler.h9
-rw-r--r--src/soc/intel/common/block/smm/smihandler.c42
-rw-r--r--src/soc/intel/icelake/smihandler.c42
-rw-r--r--src/soc/intel/skylake/smihandler.c39
-rw-r--r--src/soc/intel/tigerlake/smihandler.c42
7 files changed, 44 insertions, 185 deletions
diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c
index 424d66f0d7..e37de92d2a 100644
--- a/src/soc/intel/apollolake/smihandler.c
+++ b/src/soc/intel/apollolake/smihandler.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015-2016 Intel Corp.
+ * Copyright (C) 2015-2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -34,16 +34,6 @@ const struct smm_save_state_ops *get_smm_save_state_ops(void)
return &em64t100_smm_ops;
}
-/* SMI handlers that should be serviced in SCI mode too. */
-uint32_t smihandler_soc_get_sci_mask(void)
-{
- uint32_t sci_mask =
- SMI_HANDLER_SCI_EN(APM_STS_BIT) |
- SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
-
- return sci_mask;
-}
-
const smi_handler_t southbridge_smi[32] = {
[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
[APM_STS_BIT] = smihandler_southbridge_apmc,
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
index 4d0b241517..550c92dc6f 100644
--- a/src/soc/intel/cannonlake/smihandler.c
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -3,7 +3,7 @@
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,26 +17,19 @@
#include <console/console.h>
#include <device/pci_def.h>
-#include <intelblocks/fast_spi.h>
+#include <intelblocks/cse.h>
#include <intelblocks/p2sb.h>
#include <intelblocks/pcr.h>
#include <intelblocks/smihandler.h>
-#include <soc/p2sb.h>
+#include <soc/soc_chip.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
#include <soc/pm.h>
-#include "chip.h"
-
#define CSME0_FBE 0xf
#define CSME0_BAR 0x0
#define CSME0_FID 0xb0
-const struct smm_save_state_ops *get_smm_save_state_ops(void)
-{
- return &em64t101_smm_ops;
-}
-
static void pch_disable_heci(void)
{
struct pcr_sbi_msg msg = {
@@ -85,36 +78,6 @@ void smihandler_soc_at_finalize(void)
pch_disable_heci();
}
-void smihandler_soc_check_illegal_access(uint32_t tco_sts)
-{
- if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM)
- && fast_spi_wpd_status()))
- return;
-
- /*
- * BWE is RW, so the SMI was caused by a
- * write to BWE, not by a write to the BIOS
- *
- * This is the place where we notice someone
- * is trying to tinker with the BIOS. We are
- * trying to be nice and just ignore it. A more
- * resolute answer would be to power down the
- * box.
- */
- printk(BIOS_DEBUG, "Switching back to RO\n");
- fast_spi_enable_wp();
-}
-
-/* SMI handlers that should be serviced in SCI mode too. */
-uint32_t smihandler_soc_get_sci_mask(void)
-{
- uint32_t sci_mask =
- SMI_HANDLER_SCI_EN(APM_STS_BIT) |
- SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
-
- return sci_mask;
-}
-
const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
[APM_STS_BIT] = smihandler_southbridge_apmc,
diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h
index d8520f12c6..06b9e212ad 100644
--- a/src/soc/intel/common/block/include/intelblocks/smihandler.h
+++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h
@@ -156,15 +156,6 @@ void smihandler_soc_at_finalize(void);
*/
int smihandler_soc_disable_busmaster(pci_devfn_t dev);
-/* SMI handlers that should be serviced in SCI mode too. */
-uint32_t smihandler_soc_get_sci_mask(void);
-
-/*
- * SoC needs to implement the mechanism to know if an illegal attempt
- * has been made to write to the BIOS area.
- */
-void smihandler_soc_check_illegal_access(uint32_t tco_sts);
-
/* Mainboard overrides. */
/* Mainboard handler for GPI SMIs */
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 4677d27943..54f4e41e50 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015-2017 Intel Corp.
+ * Copyright (C) 2015-2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -44,6 +44,11 @@ static struct global_nvs_t *gnvs;
/* SoC overrides. */
+__weak const struct smm_save_state_ops *get_smm_save_state_ops(void)
+{
+ return &em64t101_smm_ops;
+}
+
/* Specific SOC SMI handler during ramstage finalize phase */
__weak void smihandler_soc_at_finalize(void)
{
@@ -55,20 +60,29 @@ __weak int smihandler_soc_disable_busmaster(pci_devfn_t dev)
return 1;
}
-/* SMI handlers that should be serviced in SCI mode too. */
-__weak uint32_t smihandler_soc_get_sci_mask(void)
-{
- return 0; /* No valid SCI mask for SMI handler */
-}
-
/*
* Needs to implement the mechanism to know if an illegal attempt
* has been made to write to the BIOS area.
*/
-__weak void smihandler_soc_check_illegal_access(
+static void smihandler_soc_check_illegal_access(
uint32_t tco_sts)
{
- return;
+ if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM)
+ && fast_spi_wpd_status()))
+ return;
+
+ /*
+ * BWE is RW, so the SMI was caused by a
+ * write to BWE, not by a write to the BIOS
+ *
+ * This is the place where we notice someone
+ * is trying to tinker with the BIOS. We are
+ * trying to be nice and just ignore it. A more
+ * resolute answer would be to power down the
+ * box.
+ */
+ printk(BIOS_DEBUG, "Switching back to RO\n");
+ fast_spi_enable_wp();
}
/* Mainboard overrides. */
@@ -472,6 +486,16 @@ void smihandler_southbridge_espi(
mainboard_smi_espi_handler();
}
+/* SMI handlers that should be serviced in SCI mode too. */
+static uint32_t smihandler_soc_get_sci_mask(void)
+{
+ uint32_t sci_mask =
+ SMI_HANDLER_SCI_EN(APM_STS_BIT) |
+ SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
+
+ return sci_mask;
+}
+
void southbridge_smi_handler(void)
{
int i;
diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c
index b7c37d4aa7..5228f5d4a0 100644
--- a/src/soc/intel/icelake/smihandler.c
+++ b/src/soc/intel/icelake/smihandler.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2018 Intel Corp.
+ * Copyright (C) 2018-2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,25 +15,19 @@
#include <console/console.h>
#include <device/pci_def.h>
-#include <intelblocks/fast_spi.h>
+#include <intelblocks/cse.h>
#include <intelblocks/p2sb.h>
#include <intelblocks/pcr.h>
#include <intelblocks/smihandler.h>
-#include <soc/p2sb.h>
+#include <soc/soc_chip.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
#include <soc/pm.h>
-#include <soc/soc_chip.h>
#define CSME0_FBE 0xf
#define CSME0_BAR 0x0
#define CSME0_FID 0xb0
-const struct smm_save_state_ops *get_smm_save_state_ops(void)
-{
- return &em64t101_smm_ops;
-}
-
static void pch_disable_heci(void)
{
struct pcr_sbi_msg msg = {
@@ -82,36 +76,6 @@ void smihandler_soc_at_finalize(void)
pch_disable_heci();
}
-void smihandler_soc_check_illegal_access(uint32_t tco_sts)
-{
- if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM)
- && fast_spi_wpd_status()))
- return;
-
- /*
- * BWE is RW, so the SMI was caused by a
- * write to BWE, not by a write to the BIOS
- *
- * This is the place where we notice someone
- * is trying to tinker with the BIOS. We are
- * trying to be nice and just ignore it. A more
- * resolute answer would be to power down the
- * box.
- */
- printk(BIOS_DEBUG, "Switching back to RO\n");
- fast_spi_enable_wp();
-}
-
-/* SMI handlers that should be serviced in SCI mode too. */
-uint32_t smihandler_soc_get_sci_mask(void)
-{
- uint32_t sci_mask =
- SMI_HANDLER_SCI_EN(APM_STS_BIT) |
- SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
-
- return sci_mask;
-}
-
const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
[APM_STS_BIT] = smihandler_southbridge_apmc,
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index 2e93075f7b..4818c0202e 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -3,7 +3,7 @@
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2017 Intel Corporation.
+ * Copyright (C) 2015-2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,46 +15,9 @@
* GNU General Public License for more details.
*/
-#include <console/console.h>
-#include <intelblocks/fast_spi.h>
#include <intelblocks/smihandler.h>
#include <soc/pm.h>
-const struct smm_save_state_ops *get_smm_save_state_ops(void)
-{
- return &em64t101_smm_ops;
-}
-
-void smihandler_soc_check_illegal_access(uint32_t tco_sts)
-{
- if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM)
- && fast_spi_wpd_status()))
- return;
-
- /*
- * BWE is RW, so the SMI was caused by a
- * write to BWE, not by a write to the BIOS
- *
- * This is the place where we notice someone
- * is trying to tinker with the BIOS. We are
- * trying to be nice and just ignore it. A more
- * resolute answer would be to power down the
- * box.
- */
- printk(BIOS_DEBUG, "Switching back to RO\n");
- fast_spi_enable_wp();
-}
-
-/* SMI handlers that should be serviced in SCI mode too. */
-uint32_t smihandler_soc_get_sci_mask(void)
-{
- uint32_t sci_mask =
- SMI_HANDLER_SCI_EN(APM_STS_BIT) |
- SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
-
- return sci_mask;
-}
-
const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
[APM_STS_BIT] = smihandler_southbridge_apmc,
diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c
index bf07beadb6..68954eb999 100644
--- a/src/soc/intel/tigerlake/smihandler.c
+++ b/src/soc/intel/tigerlake/smihandler.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
+ * Copyright (C) 2019-2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,25 +15,19 @@
#include <console/console.h>
#include <device/pci_def.h>
-#include <intelblocks/fast_spi.h>
+#include <intelblocks/cse.h>
#include <intelblocks/p2sb.h>
#include <intelblocks/pcr.h>
#include <intelblocks/smihandler.h>
-#include <soc/p2sb.h>
+#include <soc/soc_chip.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
#include <soc/pm.h>
-#include <soc/soc_chip.h>
#define CSME0_FBE 0xf
#define CSME0_BAR 0x0
#define CSME0_FID 0xb0
-const struct smm_save_state_ops *get_smm_save_state_ops(void)
-{
- return &em64t101_smm_ops;
-}
-
static void pch_disable_heci(void)
{
struct pcr_sbi_msg msg = {
@@ -82,36 +76,6 @@ void smihandler_soc_at_finalize(void)
pch_disable_heci();
}
-void smihandler_soc_check_illegal_access(uint32_t tco_sts)
-{
- if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM)
- && fast_spi_wpd_status()))
- return;
-
- /*
- * BWE is RW, so the SMI was caused by a
- * write to BWE, not by a write to the BIOS
- *
- * This is the place where we notice someone
- * is trying to tinker with the BIOS. We are
- * trying to be nice and just ignore it. A more
- * resolute answer would be to power down the
- * box.
- */
- printk(BIOS_DEBUG, "Switching back to RO\n");
- fast_spi_enable_wp();
-}
-
-/* SMI handlers that should be serviced in SCI mode too. */
-uint32_t smihandler_soc_get_sci_mask(void)
-{
- uint32_t sci_mask =
- SMI_HANDLER_SCI_EN(APM_STS_BIT) |
- SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
-
- return sci_mask;
-}
-
const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
[APM_STS_BIT] = smihandler_southbridge_apmc,