Revert "samsung/exynos5: add resource functions for the display port"

This reverts commit 9427ca151e44644238b1b52138894195a9f5175f

Looks like we were a bit too anxious to see this one get in. The devicetree.cb change seems to have broken things.
coreboot memory table:
 0. 0000000050000000-000000005000ffff: RESERVED
 1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES
 2. 0000014004000000-00000140044007ff: RESERVED

Before this patch:
coreboot memory table:
 0. 0000000040000000-00000000bfefffff: RAM
 1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES

Change-Id: I618e4f1976265d56cfd6a61d0c5736c55a0f3cec
Reviewed-on: http://review.coreboot.org/2914
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>

7 files changed, 143 insertions, 102 deletions

diff --git a/src/cpu/samsung/exynos5-common/displayport/Kconfig b/src/cpu/samsung/exynos5-common/displayport/Kconfig
new file mode 100644
index 0000000000..26d1422a8c
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/displayport/Kconfig
@@ -0,0 +1,2 @@
+config EXYNOS_DISPLAYPORT
+	bool
diff --git a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc
new file mode 100644
index 0000000000..7c52eaf6f7
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc
@@ -0,0 +1,2 @@
+ramstage-$(CONFIG_EXYNOS_DISPLAYPORT) += displayport.c
+
diff --git a/src/cpu/samsung/exynos5250/chip.h b/src/cpu/samsung/exynos5-common/displayport/chip.h
index 798cd26f7a..53b7836268 100644
--- a/src/cpu/samsung/exynos5250/chip.h
+++ b/src/cpu/samsung/exynos5-common/displayport/chip.h
@@ -17,10 +17,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef CPU_SAMSUNG_EXYNOS5250_H
-#define CPU_SAMSUNG_EXYNOS5250_H
+#ifndef CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H
+#define CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H
 
-struct cpu_samsung_exynos5250_config {
+struct cpu_samsung_exynos5_common_displayport_config {
 	/* special magic numbers! */
 	int clkval_f;
 	int upper_margin;
@@ -37,4 +37,4 @@ struct cpu_samsung_exynos5250_config {
 	u32 lcdbase;
 };
 
-#endif /* CPU_SAMSUNG_EXYNOS5250_H */
+#endif /* CPU_SAMSUNG_EXYNOS5-COMMON_DISPLAYPORT_H */
diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c
new file mode 100644
index 0000000000..1c08bc710e
--- /dev/null
+++ b/src/cpu/samsung/exynos5-common/displayport/displayport.c
@@ -0,0 +1,107 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include <delay.h>
+#include <arch/io.h>
+#include <device/device.h>
+
+/* we distinguish a display port device from a raw graphics device because there are
+ * dramatic differences in startup depending on graphics usage. To make startup fast
+ * and easier to understand and debug we explicitly name this common case. The alternate
+ * approach, involving lots of machine and callbacks, is hard to debug and verify.
+ */
+static void exynos_displayport_init(void)
+{
+	struct cpu_samsung_exynos5_common_displayport_config *conf = dev->chip_info;
+	/* put these on the stack. If, at some point, we want to move this code to a
+	 * pre-ram stage, it will be much easier.
+	 */
+	vidinfo_t vi;
+	struct exynos5_fimd_panel panel;
+	void *lcdbase;
+
+	memset(vi, 0, sizeof(vi));
+	memset(panel, 0, sizeof(panel));
+
+	panel.is_dp = 1; /* Display I/F is eDP */
+	/* while it is true that we did a memset to zero,
+	 * we leave some 'set to zero' entries here to make
+	 * it clear what's going on. Graphics is confusing.
+	 */
+	panel.is_mipi = 0;
+	panel.fixvclk = 0;
+	panel.ivclk = 0;
+	panel.clkval_f = conf->clkval_f;
+	panel.upper_margin = conf->upper_margin;
+	panel.lower_margin = conf->lower_margin;
+	panel.vsync = conf->vsync;
+	panel.left_margin = conf->left_margin;
+	panel.right_margin = conf->right_margin;
+	panel.hsync = conf->hsync;
+
+	vi->vl_col = conf->xres;
+	vi->fl_row = conf->yres;
+	vi->vl_bpix = conf->bpp;
+	vi->cmap = cbmem_reserve(64*1024); /* The size is a magic number from hardware. */
+
+	lcdbase = conf->lcdbase;
+	printk(BIOS_DEBUG, "Initializing exynos VGA\n");
+	ret = lcd_ctrl_init(&vi, &panel, lcdbase);
+#if 0
+	ret = board_dp_lcd_vdd(blob, &wait_ms);
+	ret = board_dp_bridge_setup(blob, &wait_ms);
+	while (tries < 5) {
+		ret = board_dp_bridge_init(blob, &wait_ms);
+		ret = board_dp_hotplug(blob, &wait_ms);
+		if (ret) {
+			ret = board_dp_bridge_reset(blob, &wait_ms);
+			continue;
+		}
+		ret = dp_controller_init(blob, &wait_ms);
+		ret = board_dp_backlight_vdd(blob, &wait_ms);
+		ret = board_dp_backlight_pwm(blob, &wait_ms);
+		ret = board_dp_backlight_en(blob, &wait_ms);
+	}
+#endif
+}
+
+static void exynos_displayport_noop(device_t dummy)
+{
+}
+
+static struct device_operations exynos_displayport_operations  = {
+	.read_resources   = exynos_displayport_noop,
+	.set_resources    = exynos_displayport_noop,
+	.enable_resources = exynos_displayport_noop,
+	.init		  = exynos_displayport_init,
+	.scan_bus	  = exynos_displayport_noop,
+};
+
+static void exynos_displayport_enable(struct device *dev)
+{
+	if (dev->link_list != NULL)
+		dev->ops = &exynos_displayport_operations;
+}
+
+struct chip_operations drivers_i2c_exynos_displayport_ops = {
+	CHIP_NAME("exynos displayport")
+	.enable_dev = exynos_displayport_enable;
+};
diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c
index 990a313639..30d0767923 100644
--- a/src/cpu/samsung/exynos5-common/exynos-fb.c
+++ b/src/cpu/samsung/exynos5-common/exynos-fb.c
@@ -100,7 +100,7 @@ static void fimd_bypass(void)
 {
 	struct exynos5_sysreg *sysreg = samsung_get_base_sysreg();
 
-	setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);
+	/*setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);*/
 	sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1;
 }
 
@@ -586,9 +586,7 @@ int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data,
 	//vi->yres = panel_info->vl_row;
 
 	fimd_bypass();
-	printk(BIOS_SPEW, "fimd_bypass\n");
 	fb_init(panel_info, lcdbase, panel_data);
-	printk(BIOS_SPEW, "fb_init(%p, %p, %p\n",panel_info, lcdbase, panel_data);
 
 	/* Enable flushing after LCD writes if requested */
 	// forget it. lcd_set_flush_dcache(1);
diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c
index 114d6916de..bcf4d22dbd 100644
--- a/src/cpu/samsung/exynos5250/cpu.c
+++ b/src/cpu/samsung/exynos5250/cpu.c
@@ -1,14 +1,5 @@
-#include <stdlib.h>
-#include <string.h>
-#include <stddef.h>
-#include <delay.h>
 #include <console/console.h>
-#include <arch/io.h>
 #include <device/device.h>
-#include <cbmem.h>
-#include <cpu/samsung/exynos5250/fimd.h>
-#include <cpu/samsung/exynos5-common/s5p-dp-core.h>
-#include "chip.h"
 
 #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10)
 #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL)
@@ -37,76 +28,8 @@ static struct device_operations domain_ops = {
 	.scan_bus         = domain_scan_bus,
 };
 
-/* we distinguish a display port device from a raw graphics device because there are
- * dramatic differences in startup depending on graphics usage. To make startup fast
- * and easier to understand and debug we explicitly name this common case. The alternate
- * approach, involving lots of machine and callbacks, is hard to debug and verify.
- */
-static void exynos_displayport_init(device_t dev)
-{
-	int ret;
-	struct cpu_samsung_exynos5250_config *conf = dev->chip_info;
-	/* put these on the stack. If, at some point, we want to move this code to a
-	 * pre-ram stage, it will be much easier.
-	 */
-	vidinfo_t vi;
-	struct exynos5_fimd_panel panel;
-	u32 lcdbase;
-
-	printk(BIOS_SPEW, "%s: dev %p, conf %p\n", __func__, dev, conf);
-	memset(&vi, 0, sizeof(vi));
-	memset(&panel, 0, sizeof(panel));
-
-	panel.is_dp = 1; /* Display I/F is eDP */
-	/* while it is true that we did a memset to zero,
-	 * we leave some 'set to zero' entries here to make
-	 * it clear what's going on. Graphics is confusing.
-	 */
-	panel.is_mipi = 0;
-	panel.fixvclk = 0;
-	panel.ivclk = 0;
-	panel.clkval_f = conf->clkval_f;
-	panel.upper_margin = conf->upper_margin;
-	panel.lower_margin = conf->lower_margin;
-	panel.vsync = conf->vsync;
-	panel.left_margin = conf->left_margin;
-	panel.right_margin = conf->right_margin;
-	panel.hsync = conf->hsync;
-
-	vi.vl_col = conf->xres;
-	vi.vl_row = conf->yres;
-	vi.vl_bpix = conf->bpp;
-	printk(BIOS_SPEW, "lcd base is %p\n", (void *)(conf->lcdbase));
-	/* The size is a magic number from hardware. */
-	mmio_resource(dev, 0, conf->lcdbase/KiB, 64);
-	vi.cmap = (void *)conf->lcdbase;
-	lcdbase = conf->lcdbase + 64*KiB;
-
-	mmio_resource(dev, 1, lcdbase, (conf->xres*conf->yres*4 + (KiB-1))/KiB);
-	printk(BIOS_DEBUG, "Initializing exynos VGA, base %p\n",(void *)lcdbase);
-	ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase);
-#if 0
-	ret = board_dp_lcd_vdd(blob, &wait_ms);
-	ret = board_dp_bridge_setup(blob, &wait_ms);
-	while (tries < 5) {
-		ret = board_dp_bridge_init(blob, &wait_ms);
-		ret = board_dp_hotplug(blob, &wait_ms);
-		if (ret) {
-			ret = board_dp_bridge_reset(blob, &wait_ms);
-			continue;
-		}
-		ret = dp_controller_init(blob, &wait_ms);
-		ret = board_dp_backlight_vdd(blob, &wait_ms);
-		ret = board_dp_backlight_pwm(blob, &wait_ms);
-		ret = board_dp_backlight_en(blob, &wait_ms);
-	}
-#endif
-}
-
 static void cpu_init(device_t dev)
 {
-	printk(BIOS_SPEW, "%s\n", __func__);
-	exynos_displayport_init(dev);
 }
 
 static void cpu_noop(device_t dev)
@@ -121,20 +44,17 @@ static struct device_operations cpu_ops = {
 	.scan_bus         = 0,
 };
 
-static void enable_exynos5250_dev(device_t dev)
+static void enable_dev(device_t dev)
 {
 	/* Set the operations if it is a special bus type */
 	if (dev->path.type == DEVICE_PATH_DOMAIN) {
-		printk(BIOS_SPEW, "%s: DOMAIN\n", __func__);
 		dev->ops = &domain_ops;
 	} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
-		printk(BIOS_SPEW, "%s: CPU_CLUSTER\n", __func__);
 		dev->ops = &cpu_ops;
 	}
-	printk(BIOS_SPEW, "%s: done\n", __func__);
 }
 
 struct chip_operations cpu_samsung_exynos5250_ops = {
 	CHIP_NAME("CPU Samsung Exynos 5250")
-	.enable_dev = enable_exynos5250_dev,
+	.enable_dev = enable_dev,
 };
diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb
index cfe5cf183d..5ad786ef55 100644
--- a/src/mainboard/google/snow/devicetree.cb
+++ b/src/mainboard/google/snow/devicetree.cb
@@ -17,18 +17,30 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+# FIXME: this is just a stub for now
 chip cpu/samsung/exynos5250
-	device cpu_cluster 0 on end
-	register "xres" = "1366"
-	register "yres" = "768"
-	register "bpp" = "16"
-	# complex magic timing!
-	register "clkval_f" = "2"
-	register "upper_margin" = "14"
-	register "lower_margin" = "3"
-	register "vsync" = "5"
-	register "left_margin" = "80"
-	register "right_margin" = "48"
-	register "hsync" = "32"
-	register "lcdbase" = "0x50000000"
+
+device cpu_cluster 0 on
+end
+
+device domain 0 on
+	chip drivers/generic/generic # I2C0 controller
+		device i2c 6 on end # ?
+		device i2c 9 on end # ?
+	end
+	chip cpu/samsung/exynos5-common/displayport
+		register "xres" = "1366"
+		register "yres" = "768"
+		register "bpp" = "16"
+		# complex magic timing!
+		register "clkval_f" = "2"
+		register "upper_margin" = "14"
+		register "lower_margin" = "3"
+		register "vsync" = "5"
+		register "left_margin" = "80"
+		register "right_margin" = "48"
+		register "hsync" = "32"
+		register "lcdbase" = "0x10000000"
+	end
+end
 end