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authorGarrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>2018-03-06 08:40:25 -0600
committerMartin Roth <martinroth@google.com>2018-03-07 17:54:47 +0000
commit050b6fb125d862e93719aba0ec8e8972415ece76 (patch)
tree1b90bfafed6261223a2038f03b1d61319cabb4ee /src
parent067a340117e37c5814a4f08128d831153539b54f (diff)
downloadcoreboot-050b6fb125d862e93719aba0ec8e8972415ece76.tar.xz
soc/amd/stoneyridge: Add southbridge definitions
* Add definitions to iomap.h for AMD ACPI MMIO base addresses. * Add FCH AOAC registers for enabling FCH devices. * From: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h, Models 70h-7Fh Processors Rev 3.04 BUG=b:69220826 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt Change-Id: I45c1d1d7edc864000282c7ca4e2b8f2a14ea9eac Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/24998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/iomap.h4
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h40
2 files changed, 44 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index 8dc27fb701..01171c3cf8 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -37,7 +37,11 @@
#define APU_SMI_BASE 0xfed80200
#define PM_MMIO_BASE 0xfed80300
#define BIOSRAM_MMIO_BASE 0xfed80500
+#define IOMUX_MMIO_BASE 0xfed80d00
+#define MISC_MMIO_BASE 0xfed80e00
#define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00
+#define AOAC_MMIO_BASE 0xfed81e00
+
#define APU_UART0_BASE 0xfedc6000
#define APU_UART1_BASE 0xfedc8000
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 3011af27f1..b4c7089773 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -289,6 +289,46 @@
#define GPIO_TABLE_BOOTBLOCK 0
#endif
+/* FCH AOAC Registers 0xfed81e00 */
+#define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40
+#define FCH_AOAC_D3_CONTROL_I2C0 0x4A
+#define FCH_AOAC_D3_CONTROL_I2C1 0x4C
+#define FCH_AOAC_D3_CONTROL_I2C2 0x4E
+#define FCH_AOAC_D3_CONTROL_I2C3 0x50
+#define FCH_AOAC_D3_CONTROL_UART0 0x56
+#define FCH_AOAC_D3_CONTROL_UART1 0x58
+#define FCH_AOAC_D3_CONTROL_AMBA 0x62
+#define FCH_AOAC_D3_CONTROL_USB2 0x64
+#define FCH_AOAC_D3_CONTROL_USB3 0x6E
+/* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */
+#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
+#define FCH_AOAC_DEVICE_STATE BIT(2)
+#define FCH_AOAC_PWR_ON_DEV BIT(3)
+#define FCH_AOAC_SW_PWR_ON_RSTB BIT(4)
+#define FCH_AOAC_SW_REF_CLK_OK BIT(5)
+#define FCH_AOAC_SW_RST_B BIT(6)
+#define FCH_AOAC_IS_SW_CONTROL BIT(7)
+
+#define FCH_AOAC_D3_STATE_CLK_GEN 0x41
+#define FCH_AOAC_D3_STATE_I2C0 0x4B
+#define FCH_AOAC_D3_STATE_I2C1 0x4D
+#define FCH_AOAC_D3_STATE_I2C2 0x4F
+#define FCH_AOAC_D3_STATE_I2C3 0x51
+#define FCH_AOAC_D3_STATE_UART0 0x57
+#define FCH_AOAC_D3_STATE_UART1 0x59
+#define FCH_AOAC_D3_STATE_AMBA 0x63
+#define FCH_AOAC_D3_STATE_USB2 0x65
+#define FCH_AOAC_D3_STATE_USB3 0x6F
+/* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */
+#define FCH_AOAC_PWR_RST_STATE BIT(0)
+#define FCH_AOAC_RST_CLK_OK_STATE BIT(1)
+#define FCH_AOAC_RST_B_STATE BIT(2)
+#define FCH_AOAC_DEV_OFF_GATING_STATE BIT(3)
+#define FCH_AOAC_D3COLD BIT(4)
+#define FCH_AOAC_CLK_OK_STATE BIT(5)
+#define FCH_AOAC_STAT0 BIT(6)
+#define FCH_AOAC_STAT1 BIT(7)
+
struct soc_amd_stoneyridge_gpio {
uint8_t gpio;
uint8_t function;