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authorPaul Menzel <paulepanter@users.sourceforge.net>2013-05-14 09:28:26 +0200
committerBruce Griffith <Bruce.Griffith@se-eng.com>2013-05-16 06:06:50 +0200
commit05f3b117dd44776ed17bc57318f260766039b7e8 (patch)
treeb6afafa951bcc0ee035819ba47b68739e19e91d4 /src
parent5b54d353aa89685c1cde0d6254a9899cf327a712 (diff)
downloadcoreboot-05f3b117dd44776ed17bc57318f260766039b7e8.tar.xz
AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer
The following commit commit d0790694b0a66353e5531715648ddaa1a6d577cb Author: Kerry Sheh <shekairui@gmail.com> Date: Thu Jan 19 13:18:37 2012 +0800 Inagua: Inagua GNB ddi lanes and pcie lanes config update Reviewed-on: http://review.coreboot.org/544 assigns lanes 4 and 5 to PCI device number 4, but does not adapt the rest of the code. After the commit above, the array `PortList []` only has four elements, but the buffer size `AllocHeapParams.RequestedBufferSize` is set to a size as it still has five elements. Correct that by setting the size for four array elements. [1] http://review.coreboot.org/#/c/3239/3/src/mainboard/amd/inagua/PlatformGnbPcie.c Change-Id: I3ff07f308ffd417d2bf73117eda9da2a1a05f199 Reported-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3246 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/amd/inagua/PlatformGnbPcie.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c
index ac5eca3da8..20351ac35d 100644
--- a/src/mainboard/amd/inagua/PlatformGnbPcie.c
+++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c
@@ -109,7 +109,7 @@ OemCustomizeInitEarly (
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) +
- sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
+ sizeof (PCIe_PORT_DESCRIPTOR) * 4 +
sizeof (PCIe_DDI_DESCRIPTOR) * 2;
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;