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authorJulius Werner <jwerner@chromium.org>2014-10-20 13:22:00 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-04-07 19:38:03 +0200
commit0812568b5aa8ea29ce108f0ce64819cb667a5f5f (patch)
tree938bfd8f6b3d26a2cb76fcd338c8bfa1d5d133ee /src
parent80af442cd21eaa924840614b00c082b9b29abff1 (diff)
downloadcoreboot-0812568b5aa8ea29ce108f0ce64819cb667a5f5f.tar.xz
pistachio: Change all SoC headers to <soc/headername.h> system
This patch aligns pistachio to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Urara. Change-Id: I0609b307695ba6a922384ac34dd604bffcb20692 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0a577918babf26adf10baa0f56a7065f5659d285 Original-Change-Id: I3ed405a3efdeec28965538d19a22f2b5b8204f01 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224503 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/urara/memlayout.ld2
-rw-r--r--src/soc/imgtec/pistachio/Makefile.inc2
-rw-r--r--src/soc/imgtec/pistachio/include/soc/cpu.h (renamed from src/soc/imgtec/pistachio/cpu.h)0
-rw-r--r--src/soc/imgtec/pistachio/include/soc/memlayout.ld (renamed from src/soc/imgtec/pistachio/memlayout.ld)0
-rw-r--r--src/soc/imgtec/pistachio/include/soc/spi.h (renamed from src/soc/imgtec/pistachio/spi.h)0
-rw-r--r--src/soc/imgtec/pistachio/spi.c4
6 files changed, 5 insertions, 3 deletions
diff --git a/src/mainboard/google/urara/memlayout.ld b/src/mainboard/google/urara/memlayout.ld
index ab0b4dd8ff..ead7f47838 100644
--- a/src/mainboard/google/urara/memlayout.ld
+++ b/src/mainboard/google/urara/memlayout.ld
@@ -1 +1 @@
-#include <soc/imgtec/pistachio/memlayout.ld>
+#include <soc/memlayout.ld>
diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc
index d052c8f435..e955968ddc 100644
--- a/src/soc/imgtec/pistachio/Makefile.inc
+++ b/src/soc/imgtec/pistachio/Makefile.inc
@@ -42,6 +42,8 @@ romstage-y += romstage.c
romstage-y += monotonic_timer.c
romstage-y += timestamp.c
+CPPFLAGS_common += -Isrc/soc/imgtec/pistachio/include/
+
# Generate the actual coreboot bootblock code
$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
diff --git a/src/soc/imgtec/pistachio/cpu.h b/src/soc/imgtec/pistachio/include/soc/cpu.h
index c61c58dfca..c61c58dfca 100644
--- a/src/soc/imgtec/pistachio/cpu.h
+++ b/src/soc/imgtec/pistachio/include/soc/cpu.h
diff --git a/src/soc/imgtec/pistachio/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 21c3d73d5f..21c3d73d5f 100644
--- a/src/soc/imgtec/pistachio/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
diff --git a/src/soc/imgtec/pistachio/spi.h b/src/soc/imgtec/pistachio/include/soc/spi.h
index 91d6d558e5..91d6d558e5 100644
--- a/src/soc/imgtec/pistachio/spi.h
+++ b/src/soc/imgtec/pistachio/include/soc/spi.h
diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c
index 2b21475d0a..69682d0456 100644
--- a/src/soc/imgtec/pistachio/spi.c
+++ b/src/soc/imgtec/pistachio/spi.c
@@ -16,10 +16,10 @@
#include <string.h>
#include <stdlib.h>
#include <timer.h>
+#include <soc/cpu.h>
+#include <soc/spi.h>
#include <spi-generic.h>
#include <spi_flash.h>
-#include "cpu.h"
-#include "spi.h"
#if !CONFIG_SPI_ATOMIC_SEQUENCING
#error "Unsupported SPI driver API"