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authorPratik Prajapati <pratikkumar.v.prajapati@intel.com>2015-06-09 12:06:20 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-06-17 11:55:27 +0200
commit0cd0d28f0a4a246c0901a5e1f4685205bb683ebd (patch)
treedb199c2853b002dced00aa08c09b2cb7cf61a0a8 /src
parent121b4c09c4d0bd91564c4bcf057224b1d7d4a012 (diff)
downloadcoreboot-0cd0d28f0a4a246c0901a5e1f4685205bb683ebd.tar.xz
PCIe : Adding some error/not-null condition checking
This patch checks for following conditions (1) while enabling LTR, if PCI_CAP_ID_PCIE is don't found then don't enable LTR. (2) 2.1) set_L1_ss_latency is member if ops_pci, which could be NULL. so confirm ops_pci is not NULL before calling its member function. 2.2) if PCI_CAP_ID_PCIE is not found, then don't try to set latency. BUG=none BRANCH=none TEST=build and boot coreboot with L1 substate enabled on sklrvp3. Change-Id: I31965266f81f2a12ee719f69ed9a20b096c8b315 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3592a7c974186f2f1113cb002db4632c8f1ab181 Original-Change-Id: I95041490f9fafd2d6f57a8279614ccb7994a1447 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/276423 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/10559 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/device/pciexp_device.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c
index ee24456747..aa3a457541 100644
--- a/src/device/pciexp_device.c
+++ b/src/device/pciexp_device.c
@@ -147,15 +147,20 @@ static void pciexp_config_max_latency(device_t root, device_t dev)
{
unsigned int cap;
cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID);
- if (root->ops->ops_pci->set_L1_ss_latency != NULL)
- root->ops->ops_pci->set_L1_ss_latency(dev, cap + 4);
+ if ((cap) && (root->ops->ops_pci != NULL) &&
+ (root->ops->ops_pci->set_L1_ss_latency != NULL))
+ root->ops->ops_pci->set_L1_ss_latency(dev, cap + 4);
}
static void pciexp_enable_ltr(device_t dev)
{
unsigned int cap;
cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
-
+ if(!cap) {
+ printk(BIOS_INFO, "Failed to enable LTR for dev = %s\n",
+ dev_path(dev));
+ return;
+ }
pcie_update_cfg(dev, cap + 0x28, ~(1 << 10), 1 << 10);
}