zero warnings days...

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5484 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 13 insertions, 9 deletions

diff --git a/src/northbridge/amd/amdk8/amdk8_f_pci.c b/src/northbridge/amd/amdk8/amdk8_f_pci.c
index 607fc6c73e..d89dadc0d6 100644
--- a/src/northbridge/amd/amdk8/amdk8_f_pci.c
+++ b/src/northbridge/amd/amdk8/amdk8_f_pci.c
@@ -1,6 +1,7 @@
 #ifndef AMDK8_F_PCI_C
-
 #define AMDK8_F_PCI_C
+
+#ifdef UNUSED_CODE
 /* bit [10,8] are dev func, bit[1,0] are dev index */
 static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32_t index)
 {
@@ -15,16 +16,14 @@ static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32
 
 static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data)
 {
-
 	pci_write_config32(dev, index_reg, index);
 
 	pci_write_config32(dev, index_reg + 0x4, data);
-
 }
+#endif
 
 static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index)
 {
-
 	uint32_t dword;
 
 	index &= ~(1<<30);
@@ -41,7 +40,6 @@ static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, u
 
 static void pci_write_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data)
 {
-
 	uint32_t dword;
 
 	pci_write_config32(dev, index_reg + 0x4, data);
@@ -51,7 +49,6 @@ static void pci_write_config32_index_wait(device_t dev, uint32_t index_reg, uint
 	do {
 		dword = pci_read_config32(dev, index_reg);
 	} while (!(dword & (1<<31)));
-
 }
 
 #endif
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index ddf613ea54..5db9deafc4 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -576,6 +576,7 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
 	return reset_needed;
 }
 
+#if defined(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) || defined(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55)
 static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
 {
 	uint32_t dword;
@@ -601,6 +602,7 @@ static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt,
 
 	return 0;
 }
+
 static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid,  unsigned val)
 {
 	int reset_needed;
@@ -632,7 +634,7 @@ static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid,
 
 	return reset_needed;
 }
-
+#endif
 
 #if RAMINIT_SYSINFO == 1
 static void ht_setup_chains(uint8_t ht_c_num, struct sys_info *sysinfo)
diff --git a/src/southbridge/amd/rs690/rs690.c b/src/southbridge/amd/rs690/rs690.c
index caf838aacf..0d6db72393 100644
--- a/src/southbridge/amd/rs690/rs690.c
+++ b/src/southbridge/amd/rs690/rs690.c
@@ -104,8 +104,7 @@ void static rs690_config_misc_clk(device_t nb_dev)
 	set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
 }
 
-
-u32 get_vid_did(device_t dev)
+static u32 get_vid_did(device_t dev)
 {
 	return pci_read_config32(dev, 0);
 }
diff --git a/src/southbridge/amd/rs690/rs690_pcie.c b/src/southbridge/amd/rs690/rs690_pcie.c
index ad2e871db4..f02e0d73b4 100644
--- a/src/southbridge/amd/rs690/rs690_pcie.c
+++ b/src/southbridge/amd/rs690/rs690_pcie.c
@@ -105,6 +105,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
 	}
 }
 
+#ifdef UNUSED_CODE
 static void pcie_init(struct device *dev)
 {
 	/* Enable pci error detecting */
@@ -118,6 +119,7 @@ static void pcie_init(struct device *dev)
 	dword |= (1 << 30);	/* Clear possible errors */
 	pci_write_config32(dev, 0x04, dword);
 }
+#endif
 
 /**********************************************************************
 **********************************************************************/
@@ -355,6 +357,7 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev)
 	ValidatePortEn(nb_dev);
 }
 
+#ifdef UNUSED_CODE
 /*****************************************
 * Compliant with CIM_33's PCIEMiscClkProg
 *****************************************/
@@ -395,3 +398,4 @@ void pcie_config_misc_clk(device_t nb_dev)
 	reg &= ~(1 << 0);
 	pci_write_config32(nb_dev, 0x4c, reg);
 }
+#endif
diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup.c b/src/southbridge/nvidia/ck804/ck804_early_setup.c
index bfa0495577..fd5899a074 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_setup.c
+++ b/src/southbridge/nvidia/ck804/ck804_early_setup.c
@@ -3,6 +3,8 @@
  *  by yhlu@tyan.com
  */
 
+#include <reset.h>
+
 static int set_ht_link_ck804(uint8_t ht_c_num)
 {
 	unsigned vendorid = 0x10de;