SB800: Port to 64bit

Change-Id: I944fb254e9470c80b13c9eef9d6b1177a56e615f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10582
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>

4 files changed, 26 insertions, 17 deletions

diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c
index 70173b60f7..7a60c03852 100644
--- a/src/southbridge/amd/cimx/sb800/fadt.c
+++ b/src/southbridge/amd/cimx/sb800/fadt.c
@@ -63,8 +63,16 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	memcpy(header->asl_compiler_id, ASLC, 4);
 	header->asl_compiler_revision = 0;
 
-	fadt->firmware_ctrl = (u32) facs;
-	fadt->dsdt = (u32) dsdt;
+	if ((uintptr_t)facs > 0xffffffff)
+		printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n");
+	else
+		fadt->firmware_ctrl = (uintptr_t)facs;
+
+	if ((uintptr_t)dsdt > 0xffffffff)
+		printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n");
+	else
+		fadt->dsdt = (uintptr_t)dsdt;
+
 	fadt->model = 0;		/* reserved, should be 0 ACPI 3.0 */
 	fadt->preferred_pm_profile = FADT_PM_PROFILE;
 	fadt->sci_int = 9;		/* HUDSON 1 - IRQ 09 – ACPI SCI */
@@ -153,10 +161,10 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->res4 = 0;		/* reserved, MUST be 0 ACPI 3.0 */
 	fadt->res5 = 0;		/* reserved, MUST be 0 ACPI 3.0 */
 
-	fadt->x_firmware_ctl_l = 0;	/* set to 0 if firmware_ctrl is used */
-	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = (u32) dsdt;
-	fadt->x_dsdt_h = 0;
+	fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff;
+	fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32;
+	fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff;
+	fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32;
 
 	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_pm1a_evt_blk.bit_width = 32;
diff --git a/src/southbridge/amd/cimx/sb800/gpio_oem.h b/src/southbridge/amd/cimx/sb800/gpio_oem.h
index a9f59e3a31..e2c81fc3f7 100644
--- a/src/southbridge/amd/cimx/sb800/gpio_oem.h
+++ b/src/southbridge/amd/cimx/sb800/gpio_oem.h
@@ -11,9 +11,9 @@
 #define SB_GPIO_REG28   28
 
 /* FCH GPIO access helpers */
-#define FCH_IOMUX(gpio_nr) (*(u8*)(ACPI_MMIO_BASE+IOMUX_BASE+(gpio_nr)))
-#define FCH_PMIO(reg_nr) (*(u8*)(ACPI_MMIO_BASE+PMIO_BASE+(reg_nr)))
-#define FCH_GPIO(gpio_nr) (*(volatile u8*)(ACPI_MMIO_BASE+GPIO_BASE+(gpio_nr)))
+#define FCH_IOMUX(gpio_nr) (*(u8*)((uintptr_t)ACPI_MMIO_BASE+IOMUX_BASE+(gpio_nr)))
+#define FCH_PMIO(reg_nr) (*(u8*)((uintptr_t)ACPI_MMIO_BASE+PMIO_BASE+(reg_nr)))
+#define FCH_GPIO(gpio_nr) (*(volatile u8*)((uintptr_t)ACPI_MMIO_BASE+GPIO_BASE+(gpio_nr)))
 
 static inline u8 fch_gpio_state(unsigned int gpio_nr)
 {
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 0ada673a89..cf7fb1cc0c 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -92,7 +92,8 @@ static u32 sb800_callout_entry(u32 func, u32 data, void* config)
 static void ahci_raid_init(struct device *dev)
 {
 	u8 irq = 0;
-	u32 bar5, caps, ports, val;
+	void *bar5;
+	u32 caps, ports, val;
 
 	val = pci_read_config16(dev, PCI_CLASS_DEVICE);
 	if (val == PCI_CLASS_STORAGE_SATA) {
@@ -105,18 +106,18 @@ static void ahci_raid_init(struct device *dev)
 	}
 
 	irq = pci_read_config8(dev, PCI_INTERRUPT_LINE);
-	bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
-	printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq);
+	bar5 = (void *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+	printk(BIOS_DEBUG, "IOMEM base: %p, IRQ: 0x%X\n", bar5, irq);
 
-	caps = *(volatile u32 *)(bar5 + HOST_CAP);
+	caps = read32(bar5 + HOST_CAP);
 	caps = (caps & 0x1F) + 1;
-	ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL);
+	ports= read32(bar5 + HOST_PORTS_IMPL);
 	printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports);
 
 	/* make sure ahci is enabled */
-	val = *(volatile u32 *)(bar5 + HOST_CTL);
+	val = read32(bar5 + HOST_CTL);
 	if (!(val & HOST_CTL_AHCI_EN)) {
-		*(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN;
+		write32(bar5 + HOST_CTL, val | HOST_CTL_AHCI_EN);
 	}
 
 	dev->command |= PCI_COMMAND_MASTER;
diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c
index 1ce7fcd321..694a3b7fc8 100644
--- a/src/southbridge/amd/cimx/sb800/spi.c
+++ b/src/southbridge/amd/cimx/sb800/spi.c
@@ -35,7 +35,7 @@ static int bus_claimed = 0;
 
 #define AMD_SB_SPI_TX_LEN	8
 
-static u32 spibar;
+static uintptr_t spibar;
 
 static void reset_internal_fifo_pointer(void)
 {