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| author | Matthew Garrett <mjg59@google.com> | 2019-07-19 17:02:07 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-21 18:44:19 +0000 |
| commit | 13e7a2fd353cb07802c86f2258d41a2c5e54eab7 (patch) | |
| tree | 6fe6cd95cffe443cefdf3fdb8cdf04f2619d5f6e /src | |
| parent | bcbc514cfa9f2e6da4002693a67abf42de39336d (diff) | |
| download | coreboot-13e7a2fd353cb07802c86f2258d41a2c5e54eab7.tar.xz | |
soc/intel/skylake: Enable Energy/Performance Bias control
Bit 18 of MSR_POWER_CTL is documented as reserved, but we're setting it on
Haswell in order to enable EPB. It seems to work on SKL/KBL as well, so
do it there too.
Signed-off-by: Matthew Garrett <mjg59@google.com>
Change-Id: I83da1a57a04dac206cc67f2c256d0c102965abc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5f4ce87236..2fd01b471a 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -313,6 +313,7 @@ static void configure_misc(void) msr = rdmsr(MSR_POWER_CTL); msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 18); /* Enable Energy/Performance Bias control */ msr.lo &= ~POWER_CTL_C1E_MASK; /* Disable C1E */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); |