baytrail: Change all SoC headers to <soc/headername.h> system

This patch aligns baytrail to the new SoC header include scheme.

BUG=None
TEST=Tested with whole series. Compiled Rambi.

Change-Id: I0f0a894f6f33449756582eefa0b50bae545220db
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1216a86538517c03a7e5bca547d08ff3dbcaa083
Original-Change-Id: If5d2a609354b3d773aa3d482e682ab97422fd9d5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/222026
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9363
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>

76 files changed, 177 insertions, 177 deletions

diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c
index 3f7ddaf3da..bd9cdddf1a 100644
--- a/src/lib/reg_script.c
+++ b/src/lib/reg_script.c
@@ -31,7 +31,7 @@
 #endif
 
 #if CONFIG_SOC_INTEL_BAYTRAIL
-#include <baytrail/iosf.h>
+#include <soc/iosf.h>	/* TODO: wrap in <soc/reg_script.h, remove #ifdef? */
 #endif
 
 #define POLL_DELAY 100 /* 100us */
diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c
index 890e1df966..981116bfe4 100644
--- a/src/mainboard/google/rambi/acpi_tables.c
+++ b/src/mainboard/google/rambi/acpi_tables.c
@@ -30,9 +30,9 @@
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
-#include <baytrail/acpi.h>
-#include <baytrail/nvs.h>
-#include <baytrail/iomap.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include <soc/iomap.h>
 
 extern const unsigned char AmlCode[];
 
diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c
index 3ab30347ca..31d7de0fbe 100644
--- a/src/mainboard/google/rambi/chromeos.c
+++ b/src/mainboard/google/rambi/chromeos.c
@@ -22,7 +22,7 @@
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <baytrail/gpio.h>
+#include <soc/gpio.h>
 
 #if CONFIG_EC_GOOGLE_CHROMEEC
 #include "ec.h"
diff --git a/src/mainboard/google/rambi/fadt.c b/src/mainboard/google/rambi/fadt.c
index 0bd33e14a1..dfd258fa8b 100644
--- a/src/mainboard/google/rambi/fadt.c
+++ b/src/mainboard/google/rambi/fadt.c
@@ -18,7 +18,7 @@
  */
 
 #include <string.h>
-#include <baytrail/acpi.h>
+#include <soc/acpi.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c
index 77f56f7c94..45f536db21 100644
--- a/src/mainboard/google/rambi/gpio.c
+++ b/src/mainboard/google/rambi/gpio.c
@@ -18,7 +18,7 @@
  */
 
 #include <stdlib.h>
-#include <baytrail/gpio.h>
+#include <soc/gpio.h>
 #include "irqroute.h"
 
 /* TODO(SHAWNN): Modify gpios labeled 'INT' for interrupt handling */
diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h
index 0f4ca17acc..074e47093e 100644
--- a/src/mainboard/google/rambi/irqroute.h
+++ b/src/mainboard/google/rambi/irqroute.h
@@ -17,9 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <soc/intel/baytrail/baytrail/irq.h>
-#include <soc/intel/baytrail/baytrail/pci_devs.h>
-#include <soc/intel/baytrail/baytrail/pmc.h>
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
 
 #define PCI_DEV_PIRQ_ROUTES \
 	PCI_DEV_PIRQ_ROUTE(GFX_DEV,  A, B, C, D), \
diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c
index 7128448e33..1266390930 100644
--- a/src/mainboard/google/rambi/mainboard.c
+++ b/src/mainboard/google/rambi/mainboard.c
@@ -36,7 +36,7 @@
 #include <smbios.h>
 #include "ec.h"
 #include "onboard.h"
-#include <baytrail/gpio.h>
+#include <soc/gpio.h>
 #include <bootstate.h>
 
 void mainboard_suspend_resume(void)
diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c
index bd7646899f..7afdd2f1a5 100644
--- a/src/mainboard/google/rambi/mainboard_smi.c
+++ b/src/mainboard/google/rambi/mainboard_smi.c
@@ -25,8 +25,8 @@
 #include <ec/google/chromeec/ec.h>
 #include "ec.h"
 
-#include <baytrail/nvs.h>
-#include <baytrail/pmc.h>
+#include <soc/nvs.h>
+#include <soc/pmc.h>
 
 /* The wake gpio is SUS_GPIO[0]. */
 #define WAKE_GPIO_EN SUS_GPIO_EN0
diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c
index 7c505e73b3..0f431d93ae 100644
--- a/src/mainboard/google/rambi/romstage.c
+++ b/src/mainboard/google/rambi/romstage.c
@@ -21,9 +21,9 @@
 #include <string.h>
 #include <cbfs.h>
 #include <console/console.h>
-#include <baytrail/gpio.h>
-#include <baytrail/mrc_wrapper.h>
-#include <baytrail/romstage.h>
+#include <soc/gpio.h>
+#include <soc/mrc_wrapper.h>
+#include <soc/romstage.h>
 
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
diff --git a/src/mainboard/google/rambi/w25q64.c b/src/mainboard/google/rambi/w25q64.c
index dbc26e4732..9692b4c10a 100644
--- a/src/mainboard/google/rambi/w25q64.c
+++ b/src/mainboard/google/rambi/w25q64.c
@@ -18,7 +18,7 @@
  */
 
 #include <string.h>
-#include <baytrail/spi.h>
+#include <soc/spi.h>
 
 /*
  * SPI lockdown configuration W25Q64FW.
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index c79df34051..67ad00bebb 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -52,7 +52,7 @@ ramstage-y += hda.c
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
 
-CPPFLAGS_common += -Isrc/soc/intel/baytrail/
+CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
 
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index cefc215db2..74e7336cf4 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -33,12 +33,12 @@
 #include <cpu/x86/tsc.h>
 #include <cpu/intel/turbo.h>
 
-#include <baytrail/acpi.h>
-#include <baytrail/iomap.h>
-#include <baytrail/irq.h>
-#include <baytrail/msr.h>
-#include <baytrail/pattrs.h>
-#include <baytrail/pmc.h>
+#include <soc/acpi.h>
+#include <soc/iomap.h>
+#include <soc/irq.h>
+#include <soc/msr.h>
+#include <soc/pattrs.h>
+#include <soc/pmc.h>
 
 #include <ec/google/chromeec/ec.h>
 #include <vendorcode/google/chromeos/gnvs.h>
diff --git a/src/soc/intel/baytrail/acpi/gpio.asl b/src/soc/intel/baytrail/acpi/gpio.asl
index 5e734881ab..aa6af717c1 100644
--- a/src/soc/intel/baytrail/acpi/gpio.asl
+++ b/src/soc/intel/baytrail/acpi/gpio.asl
@@ -19,8 +19,8 @@
  * MA 02110-1301 USA
  */
 
-#include <soc/intel/baytrail/baytrail/iomap.h>
-#include <soc/intel/baytrail/baytrail/irq.h>
+#include <soc/iomap.h>
+#include <soc/irq.h>
 
 /* SouthCluster GPIO */
 Device (GPSC)
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index 354515ba67..47151a30fa 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -19,8 +19,8 @@
  * MA 02110-1301 USA
  */
 
-#include <soc/intel/baytrail/baytrail/iomap.h>
-#include <soc/intel/baytrail/baytrail/irq.h>
+#include <soc/iomap.h>
+#include <soc/irq.h>
 
 Scope(\)
 {
diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c
index 1ff9369f08..9d7f19c4c7 100644
--- a/src/soc/intel/baytrail/bootblock/bootblock.c
+++ b/src/soc/intel/baytrail/bootblock/bootblock.c
@@ -21,7 +21,7 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
-#include <baytrail/iosf.h>
+#include <soc/iosf.h>
 #include <cpu/intel/microcode/microcode.c>
 
 static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type)
diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c
index 7a5b9c22f5..281019ab95 100644
--- a/src/soc/intel/baytrail/chip.c
+++ b/src/soc/intel/baytrail/chip.c
@@ -22,8 +22,8 @@
 #include <device/pci.h>
 #include <arch/pci_ops.h>
 
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 #include "chip.h"
 
 static void pci_domain_set_resources(device_t dev)
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index e8f95ae167..f4d752eb94 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -30,11 +30,11 @@
 #include <cpu/x86/smm.h>
 #include <reg_script.h>
 
-#include <baytrail/iosf.h>
-#include <baytrail/msr.h>
-#include <baytrail/pattrs.h>
-#include <baytrail/ramstage.h>
-#include <baytrail/smm.h>
+#include <soc/iosf.h>
+#include <soc/msr.h>
+#include <soc/pattrs.h>
+#include <soc/ramstage.h>
+#include <soc/smm.h>
 
 static void smm_relocate(void *unused);
 static void enable_smis(void *unused);
diff --git a/src/soc/intel/baytrail/dptf.c b/src/soc/intel/baytrail/dptf.c
index e8753198d4..20d34209de 100644
--- a/src/soc/intel/baytrail/dptf.c
+++ b/src/soc/intel/baytrail/dptf.c
@@ -22,7 +22,7 @@
 #include <bootstate.h>
 #include <console/console.h>
 #include <reg_script.h>
-#include <baytrail/iosf.h>
+#include <soc/iosf.h>
 
 static const struct reg_script dptf_init_settings[] = {
 	/* SocThermInit */
diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c
index 74577af4a8..7cf5e2b5a9 100644
--- a/src/soc/intel/baytrail/ehci.c
+++ b/src/soc/intel/baytrail/ehci.c
@@ -25,12 +25,12 @@
 #include <stdint.h>
 #include <reg_script.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/iosf.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/ramstage.h>
-#include <baytrail/ehci.h>
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/ramstage.h>
+#include <soc/ehci.h>
 
 #include "chip.h"
 
diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c
index df907a7991..f20dc97235 100644
--- a/src/soc/intel/baytrail/elog.c
+++ b/src/soc/intel/baytrail/elog.c
@@ -28,8 +28,8 @@
 #include <device/pci.h>
 #include <device/pci_ops.h>
 #include <elog.h>
-#include <baytrail/iomap.h>
-#include <baytrail/pmc.h>
+#include <soc/iomap.h>
+#include <soc/pmc.h>
 
 static void log_power_and_resets(const struct chipset_power_state *ps)
 {
diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c
index f88614bfc5..1708428506 100644
--- a/src/soc/intel/baytrail/emmc.c
+++ b/src/soc/intel/baytrail/emmc.c
@@ -25,10 +25,10 @@
 #include <device/pci_ids.h>
 #include <reg_script.h>
 
-#include <baytrail/iosf.h>
-#include <baytrail/nvs.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/iosf.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 #include "chip.h"
 
 static const struct reg_script emmc_ops[] = {
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 5b57cc3d4f..0601e94d05 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -26,10 +26,10 @@
 #include <reg_script.h>
 #include <stdlib.h>
 
-#include <baytrail/gfx.h>
-#include <baytrail/iosf.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/gfx.h>
+#include <soc/iosf.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 
 #include "chip.h"
 
diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c
index 6a971eac76..e4cc59a4b8 100644
--- a/src/soc/intel/baytrail/gpio.c
+++ b/src/soc/intel/baytrail/gpio.c
@@ -19,9 +19,9 @@
 
 #include <device/pci.h>
 #include <console/console.h>
-#include <baytrail/gpio.h>
-#include <baytrail/pmc.h>
-#include <baytrail/smm.h>
+#include <soc/gpio.h>
+#include <soc/pmc.h>
+#include <soc/smm.h>
 
 /* GPIO-to-Pad LUTs */
 static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] =
diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c
index 9e4140dcee..dd1ba1556b 100644
--- a/src/soc/intel/baytrail/hda.c
+++ b/src/soc/intel/baytrail/hda.c
@@ -25,10 +25,10 @@
 #include <reg_script.h>
 
 #include <soc/intel/common/hda_verb.h>
-#include <baytrail/iomap.h>
-#include <baytrail/iosf.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 
 static const struct reg_script init_ops[] = {
 	/* Enable no snoop traffic. */
diff --git a/src/soc/intel/baytrail/baytrail/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h
index a8c32e4789..bdf1cb3ec4 100644
--- a/src/soc/intel/baytrail/baytrail/acpi.h
+++ b/src/soc/intel/baytrail/include/soc/acpi.h
@@ -21,7 +21,7 @@
 #define _BAYTRAIL_ACPI_H_
 
 #include <arch/acpi.h>
-#include <baytrail/nvs.h>
+#include <soc/nvs.h>
 
 void acpi_create_intel_hpet(acpi_hpet_t * hpet);
 void acpi_fill_in_fadt(acpi_fadt_t *fadt);
diff --git a/src/soc/intel/baytrail/baytrail/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h
index 1ed897f8e5..1ed897f8e5 100644
--- a/src/soc/intel/baytrail/baytrail/device_nvs.h
+++ b/src/soc/intel/baytrail/include/soc/device_nvs.h
diff --git a/src/soc/intel/baytrail/baytrail/efi_wrapper.h b/src/soc/intel/baytrail/include/soc/efi_wrapper.h
index 3304d03451..3304d03451 100644
--- a/src/soc/intel/baytrail/baytrail/efi_wrapper.h
+++ b/src/soc/intel/baytrail/include/soc/efi_wrapper.h
diff --git a/src/soc/intel/baytrail/baytrail/ehci.h b/src/soc/intel/baytrail/include/soc/ehci.h
index a1edd6dffe..a1edd6dffe 100644
--- a/src/soc/intel/baytrail/baytrail/ehci.h
+++ b/src/soc/intel/baytrail/include/soc/ehci.h
diff --git a/src/soc/intel/baytrail/baytrail/gfx.h b/src/soc/intel/baytrail/include/soc/gfx.h
index 7047dd5a6a..7047dd5a6a 100644
--- a/src/soc/intel/baytrail/baytrail/gfx.h
+++ b/src/soc/intel/baytrail/include/soc/gfx.h
diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h
index d51d6e2983..413ade2d86 100644
--- a/src/soc/intel/baytrail/baytrail/gpio.h
+++ b/src/soc/intel/baytrail/include/soc/gpio.h
@@ -22,7 +22,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
-#include <baytrail/iomap.h>
+#include <soc/iomap.h>
 
 /* #define GPIO_DEBUG */
 
diff --git a/src/soc/intel/baytrail/baytrail/iomap.h b/src/soc/intel/baytrail/include/soc/iomap.h
index 867484b178..867484b178 100644
--- a/src/soc/intel/baytrail/baytrail/iomap.h
+++ b/src/soc/intel/baytrail/include/soc/iomap.h
diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/include/soc/iosf.h
index 572630bee7..6705a7320e 100644
--- a/src/soc/intel/baytrail/baytrail/iosf.h
+++ b/src/soc/intel/baytrail/include/soc/iosf.h
@@ -21,7 +21,7 @@
 #define _BAYTRAIL_IOSF_H_
 
 #include <stdint.h>
-#include <baytrail/pci_devs.h>
+#include <soc/pci_devs.h>
 
 /*
  * The Bay Trail SoC has a message network called IOSF Sideband. The access
diff --git a/src/soc/intel/baytrail/baytrail/irq.h b/src/soc/intel/baytrail/include/soc/irq.h
index 34b3f7d995..34b3f7d995 100644
--- a/src/soc/intel/baytrail/baytrail/irq.h
+++ b/src/soc/intel/baytrail/include/soc/irq.h
diff --git a/src/soc/intel/baytrail/baytrail/lpc.h b/src/soc/intel/baytrail/include/soc/lpc.h
index 2f6256cc41..2f6256cc41 100644
--- a/src/soc/intel/baytrail/baytrail/lpc.h
+++ b/src/soc/intel/baytrail/include/soc/lpc.h
diff --git a/src/soc/intel/baytrail/baytrail/mrc_wrapper.h b/src/soc/intel/baytrail/include/soc/mrc_wrapper.h
index 355dce0706..355dce0706 100644
--- a/src/soc/intel/baytrail/baytrail/mrc_wrapper.h
+++ b/src/soc/intel/baytrail/include/soc/mrc_wrapper.h
diff --git a/src/soc/intel/baytrail/baytrail/msr.h b/src/soc/intel/baytrail/include/soc/msr.h
index 47b95434e9..47b95434e9 100644
--- a/src/soc/intel/baytrail/baytrail/msr.h
+++ b/src/soc/intel/baytrail/include/soc/msr.h
diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index c5defac31c..1ba30d57af 100644
--- a/src/soc/intel/baytrail/baytrail/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -22,7 +22,7 @@
 #define _BAYTRAIL_NVS_H_
 
 #include <vendorcode/google/chromeos/gnvs.h>
-#include <baytrail/device_nvs.h>
+#include <soc/device_nvs.h>
 
 typedef struct {
 	/* Miscellaneous */
diff --git a/src/soc/intel/baytrail/baytrail/pattrs.h b/src/soc/intel/baytrail/include/soc/pattrs.h
index 81df73e6ff..81df73e6ff 100644
--- a/src/soc/intel/baytrail/baytrail/pattrs.h
+++ b/src/soc/intel/baytrail/include/soc/pattrs.h
diff --git a/src/soc/intel/baytrail/baytrail/pci_devs.h b/src/soc/intel/baytrail/include/soc/pci_devs.h
index b3fdce234a..b3fdce234a 100644
--- a/src/soc/intel/baytrail/baytrail/pci_devs.h
+++ b/src/soc/intel/baytrail/include/soc/pci_devs.h
diff --git a/src/soc/intel/baytrail/baytrail/pcie.h b/src/soc/intel/baytrail/include/soc/pcie.h
index 92ca3c8d7f..92ca3c8d7f 100644
--- a/src/soc/intel/baytrail/baytrail/pcie.h
+++ b/src/soc/intel/baytrail/include/soc/pcie.h
diff --git a/src/soc/intel/baytrail/baytrail/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h
index 1af7ab86ce..1af7ab86ce 100644
--- a/src/soc/intel/baytrail/baytrail/pmc.h
+++ b/src/soc/intel/baytrail/include/soc/pmc.h
diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h
index a8b5fdcc61..0ed83bd1d4 100644
--- a/src/soc/intel/baytrail/baytrail/ramstage.h
+++ b/src/soc/intel/baytrail/include/soc/ramstage.h
@@ -21,7 +21,7 @@
 #define _BAYTRAIL_RAMSTAGE_H_
 
 #include <device/device.h>
-#include <chip.h>
+#include <soc/intel/baytrail/chip.h>
 
 /* The baytrail_init_pre_device() function is called prior to device
  * initialization, but it's after console and cbmem has been reinitialized. */
diff --git a/src/soc/intel/baytrail/baytrail/reset.h b/src/soc/intel/baytrail/include/soc/reset.h
index dbf0fd23cf..dbf0fd23cf 100644
--- a/src/soc/intel/baytrail/baytrail/reset.h
+++ b/src/soc/intel/baytrail/include/soc/reset.h
diff --git a/src/soc/intel/baytrail/baytrail/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h
index 5fbda3725e..f99a8e28bc 100644
--- a/src/soc/intel/baytrail/baytrail/romstage.h
+++ b/src/soc/intel/baytrail/include/soc/romstage.h
@@ -26,7 +26,7 @@
 
 #include <stdint.h>
 #include <arch/cpu.h>
-#include <baytrail/mrc_wrapper.h>
+#include <soc/mrc_wrapper.h>
 
 struct romstage_params {
 	unsigned long bist;
diff --git a/src/soc/intel/baytrail/baytrail/sata.h b/src/soc/intel/baytrail/include/soc/sata.h
index 7704c18f34..7704c18f34 100644
--- a/src/soc/intel/baytrail/baytrail/sata.h
+++ b/src/soc/intel/baytrail/include/soc/sata.h
diff --git a/src/soc/intel/baytrail/baytrail/smm.h b/src/soc/intel/baytrail/include/soc/smm.h
index 0d920fb642..0d920fb642 100644
--- a/src/soc/intel/baytrail/baytrail/smm.h
+++ b/src/soc/intel/baytrail/include/soc/smm.h
diff --git a/src/soc/intel/baytrail/baytrail/spi.h b/src/soc/intel/baytrail/include/soc/spi.h
index ef71ad5a79..ef71ad5a79 100644
--- a/src/soc/intel/baytrail/baytrail/spi.h
+++ b/src/soc/intel/baytrail/include/soc/spi.h
diff --git a/src/soc/intel/baytrail/baytrail/xhci.h b/src/soc/intel/baytrail/include/soc/xhci.h
index b317361c08..b317361c08 100644
--- a/src/soc/intel/baytrail/baytrail/xhci.h
+++ b/src/soc/intel/baytrail/include/soc/xhci.h
diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c
index c4e7626a2d..8dba823460 100644
--- a/src/soc/intel/baytrail/iosf.c
+++ b/src/soc/intel/baytrail/iosf.c
@@ -18,7 +18,7 @@
  */
 
 #include <arch/io.h>
-#include <baytrail/iosf.h>
+#include <soc/iosf.h>
 
 #if !defined(__PRE_RAM__)
 #define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12))
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
index bc467ea3e3..c23fdb2be6 100644
--- a/src/soc/intel/baytrail/lpe.c
+++ b/src/soc/intel/baytrail/lpe.c
@@ -25,14 +25,14 @@
 #include <device/pci_ids.h>
 #include <reg_script.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/iosf.h>
-#include <baytrail/lpc.h>
-#include <baytrail/nvs.h>
-#include <baytrail/pattrs.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/ramstage.h>
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/lpc.h>
+#include <soc/nvs.h>
+#include <soc/pattrs.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/ramstage.h>
 #include "chip.h"
 
 
diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c
index 3ee648a55c..caa945cc31 100644
--- a/src/soc/intel/baytrail/lpss.c
+++ b/src/soc/intel/baytrail/lpss.c
@@ -26,10 +26,10 @@
 #include <device/pci_ids.h>
 #include <reg_script.h>
 
-#include <baytrail/iosf.h>
-#include <baytrail/nvs.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/iosf.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 
 #include "chip.h"
 
diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c
index 2412820853..9a49e3550e 100644
--- a/src/soc/intel/baytrail/memmap.c
+++ b/src/soc/intel/baytrail/memmap.c
@@ -19,8 +19,8 @@
 
 #include <arch/io.h>
 #include <cbmem.h>
-#include <baytrail/iosf.h>
-#include <baytrail/smm.h>
+#include <soc/iosf.h>
+#include <soc/smm.h>
 
 uintptr_t smm_region_start(void)
 {
diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c
index 8ff9712e42..97b3bccba0 100644
--- a/src/soc/intel/baytrail/northcluster.c
+++ b/src/soc/intel/baytrail/northcluster.c
@@ -24,10 +24,10 @@
 #include <device/pci_ids.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/iosf.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 
 /* Host Memory Map:
  *
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c
index c477e22160..ff4891350e 100644
--- a/src/soc/intel/baytrail/pcie.c
+++ b/src/soc/intel/baytrail/pcie.c
@@ -24,10 +24,10 @@
 #include <device/pci_ids.h>
 #include <reg_script.h>
 
-#include <baytrail/pci_devs.h>
-#include <baytrail/pcie.h>
-#include <baytrail/ramstage.h>
-#include <baytrail/smm.h>
+#include <soc/pci_devs.h>
+#include <soc/pcie.h>
+#include <soc/ramstage.h>
+#include <soc/smm.h>
 
 #include "chip.h"
 
diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c
index dade339e46..ad5ccfedb8 100644
--- a/src/soc/intel/baytrail/perf_power.c
+++ b/src/soc/intel/baytrail/perf_power.c
@@ -22,7 +22,7 @@
 #include <bootstate.h>
 #include <console/console.h>
 #include <reg_script.h>
-#include <baytrail/iosf.h>
+#include <soc/iosf.h>
 
 #define MAKE_MASK_INCLUSIVE(msb) \
 	((1ULL << (1 + (msb))) - 1)
diff --git a/src/soc/intel/baytrail/placeholders.c b/src/soc/intel/baytrail/placeholders.c
index 9e1413da94..3495c30c72 100644
--- a/src/soc/intel/baytrail/placeholders.c
+++ b/src/soc/intel/baytrail/placeholders.c
@@ -2,7 +2,7 @@
 #include <arch/acpi.h>
 #include <cpu/cpu.h>
 #include <device/pci_rom.h>
-#include <baytrail/acpi.h>
+#include <soc/acpi.h>
 
 
 void smm_init(void) {}
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index 8295b692b7..0678fb78db 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -21,10 +21,10 @@
 #include <arch/io.h>
 #include <console/console.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
 
 #if defined(__SMM__)
 
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 9e429ab983..6c2de111dc 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -30,14 +30,14 @@
 #include <stdlib.h>
 #include <string.h>
 
-#include <baytrail/gpio.h>
-#include <baytrail/lpc.h>
-#include <baytrail/msr.h>
-#include <baytrail/nvs.h>
-#include <baytrail/pattrs.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/ramstage.h>
+#include <soc/gpio.h>
+#include <soc/lpc.h>
+#include <soc/msr.h>
+#include <soc/nvs.h>
+#include <soc/pattrs.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/ramstage.h>
 
 /* Global PATTRS */
 DEFINE_PATTRS;
diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c
index 45771e0777..b3e612ad95 100644
--- a/src/soc/intel/baytrail/refcode.c
+++ b/src/soc/intel/baytrail/refcode.c
@@ -30,8 +30,8 @@
 #include <vendorcode/google/chromeos/vboot_handoff.h>
 #endif
 
-#include <baytrail/ramstage.h>
-#include <baytrail/efi_wrapper.h>
+#include <soc/ramstage.h>
+#include <soc/efi_wrapper.h>
 
 static inline struct ramstage_cache *next_cache(struct ramstage_cache *c)
 {
diff --git a/src/soc/intel/baytrail/reset.c b/src/soc/intel/baytrail/reset.c
index a421ec9018..c4cb2abfb7 100644
--- a/src/soc/intel/baytrail/reset.c
+++ b/src/soc/intel/baytrail/reset.c
@@ -18,8 +18,8 @@
  */
 
 #include <arch/io.h>
-#include <baytrail/pmc.h>
-#include <baytrail/reset.h>
+#include <soc/pmc.h>
+#include <soc/reset.h>
 
 void cold_reset(void)
 {
diff --git a/src/soc/intel/baytrail/romstage/early_spi.c b/src/soc/intel/baytrail/romstage/early_spi.c
index 6188f075fc..2c48af1698 100644
--- a/src/soc/intel/baytrail/romstage/early_spi.c
+++ b/src/soc/intel/baytrail/romstage/early_spi.c
@@ -22,9 +22,9 @@
 #include <delay.h>
 #include <console/console.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/romstage.h>
-#include <baytrail/spi.h>
+#include <soc/iomap.h>
+#include <soc/romstage.h>
+#include <soc/spi.h>
 
 #define SPI_CYCLE_DELAY 10 				/* 10us */
 #define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY	/* 400ms */
diff --git a/src/soc/intel/baytrail/romstage/gfx.c b/src/soc/intel/baytrail/romstage/gfx.c
index 592d1feaf8..f9bb9c9e8f 100644
--- a/src/soc/intel/baytrail/romstage/gfx.c
+++ b/src/soc/intel/baytrail/romstage/gfx.c
@@ -18,9 +18,9 @@
  */
 
 #include <arch/io.h>
-#include <baytrail/gfx.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/romstage.h>
+#include <soc/gfx.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
 
 void gfx_init(void)
 {
diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c
index c58a42c37e..b41359b7ff 100644
--- a/src/soc/intel/baytrail/romstage/pmc.c
+++ b/src/soc/intel/baytrail/romstage/pmc.c
@@ -22,12 +22,12 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci_def.h>
-#include <baytrail/iomap.h>
-#include <baytrail/iosf.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/romstage.h>
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/romstage.h>
 #include "../chip.h"
 
 void tco_disable(void)
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 6f3b21e3c6..fbd38df13d 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -25,13 +25,13 @@
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <halt.h>
-#include <baytrail/gpio.h>
+#include <soc/gpio.h>
 #include <soc/intel/common/mrc_cache.h>
-#include <baytrail/iomap.h>
-#include <baytrail/iosf.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/reset.h>
-#include <baytrail/romstage.h>
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/pci_devs.h>
+#include <soc/reset.h>
+#include <soc/romstage.h>
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 91548e3edf..029fee61ee 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -34,15 +34,15 @@
 #include <romstage_handoff.h>
 #include <timestamp.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#include <baytrail/gpio.h>
-#include <baytrail/iomap.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/reset.h>
-#include <baytrail/romstage.h>
-#include <baytrail/smm.h>
-#include <baytrail/spi.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/reset.h>
+#include <soc/romstage.h>
+#include <soc/smm.h>
+#include <soc/spi.h>
 
 /* The cache-as-ram assembly file calls romstage_main() after setting up
  * cache-as-ram.  romstage_main() will then call the mainboards's
diff --git a/src/soc/intel/baytrail/romstage/uart.c b/src/soc/intel/baytrail/romstage/uart.c
index e46237ac1d..7705746b9e 100644
--- a/src/soc/intel/baytrail/romstage/uart.c
+++ b/src/soc/intel/baytrail/romstage/uart.c
@@ -18,11 +18,11 @@
  */
 
 #include <arch/io.h>
-#include <baytrail/gpio.h>
-#include <baytrail/iomap.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/romstage.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
 
 void byt_config_com1_and_enable(void)
 {
diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c
index bed57c78a0..5294207cd4 100644
--- a/src/soc/intel/baytrail/sata.c
+++ b/src/soc/intel/baytrail/sata.c
@@ -18,9 +18,9 @@
  */
 
 #include <arch/io.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
-#include <baytrail/sata.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/sata.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/device.h>
diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c
index 7efb66dba1..6400996ace 100644
--- a/src/soc/intel/baytrail/scc.c
+++ b/src/soc/intel/baytrail/scc.c
@@ -25,9 +25,9 @@
 #include <device/pci_ids.h>
 #include <reg_script.h>
 
-#include <baytrail/iosf.h>
-#include <baytrail/nvs.h>
-#include <baytrail/ramstage.h>
+#include <soc/iosf.h>
+#include <soc/nvs.h>
+#include <soc/ramstage.h>
 
 static const struct reg_script scc_start_dll[] = {
 	/* Configure master DLL. */
diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c
index 97c8628bc9..577469d3aa 100644
--- a/src/soc/intel/baytrail/sd.c
+++ b/src/soc/intel/baytrail/sd.c
@@ -24,10 +24,10 @@
 #include <device/pci_ids.h>
 #include <reg_script.h>
 
-#include <baytrail/iosf.h>
-#include <baytrail/nvs.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/ramstage.h>
+#include <soc/iosf.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
 #include "chip.h"
 
 #define CAP_OVERRIDE_LOW 0xa0
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 06419077f0..03842b2fba 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -28,9 +28,9 @@
 #include <halt.h>
 #include <spi-generic.h>
 
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/nvs.h>
 
 /* GNVS needs to be set by coreboot initiating a software SMI. */
 static global_nvs_t *gnvs;
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index 9349dfa056..bfddb6859b 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -27,9 +27,9 @@
 #include <cpu/x86/smm.h>
 #include <string.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/pmc.h>
-#include <baytrail/smm.h>
+#include <soc/iomap.h>
+#include <soc/pmc.h>
+#include <soc/smm.h>
 
 /* Save settings which will be committed in SMI functions. */
 static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT];
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index a635b0d786..8df1f1a9e6 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -31,14 +31,14 @@
 #include <pc80/mc146818rtc.h>
 #include <drivers/uart/uart8250reg.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/irq.h>
-#include <baytrail/lpc.h>
-#include <baytrail/nvs.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/ramstage.h>
-#include <baytrail/spi.h>
+#include <soc/iomap.h>
+#include <soc/irq.h>
+#include <soc/lpc.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/ramstage.h>
+#include <soc/spi.h>
 #include "chip.h"
 
 static inline void
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index cf40140e09..2795d3712b 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -31,8 +31,8 @@
 #include <device/pci_ids.h>
 #include <spi_flash.h>
 
-#include <baytrail/lpc.h>
-#include <baytrail/pci_devs.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
 
 #ifdef __SMM__
 #define pci_read_config_byte(dev, reg, targ)\
diff --git a/src/soc/intel/baytrail/stage_cache.c b/src/soc/intel/baytrail/stage_cache.c
index 3bda56d968..d51746fbd1 100644
--- a/src/soc/intel/baytrail/stage_cache.c
+++ b/src/soc/intel/baytrail/stage_cache.c
@@ -19,7 +19,7 @@
 
 #include <cbmem.h>
 #include <ramstage_cache.h>
-#include <baytrail/smm.h>
+#include <soc/smm.h>
 
 struct ramstage_cache *ramstage_cache_location(long *size)
 {
diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c
index da7e96590c..700b0985ca 100644
--- a/src/soc/intel/baytrail/tsc_freq.c
+++ b/src/soc/intel/baytrail/tsc_freq.c
@@ -20,7 +20,7 @@
 #include <stdint.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/tsc.h>
-#include <baytrail/msr.h>
+#include <soc/msr.h>
 
 unsigned bus_freq_khz(void)
 {
@@ -53,9 +53,9 @@ unsigned long tsc_freq_mhz(void)
 
 #if !defined(__SMM__)
 #if !defined(__PRE_RAM__)
-#include <baytrail/ramstage.h>
+#include <soc/ramstage.h>
 #else
-#include <baytrail/romstage.h>
+#include <soc/romstage.h>
 #endif
 
 void set_max_freq(void)
diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c
index 21a0c5fcd9..776e44cc9f 100644
--- a/src/soc/intel/baytrail/xhci.c
+++ b/src/soc/intel/baytrail/xhci.c
@@ -25,14 +25,14 @@
 #include <stdint.h>
 #include <reg_script.h>
 
-#include <baytrail/iomap.h>
-#include <baytrail/iosf.h>
-#include <baytrail/lpc.h>
-#include <baytrail/pattrs.h>
-#include <baytrail/pci_devs.h>
-#include <baytrail/pmc.h>
-#include <baytrail/ramstage.h>
-#include <baytrail/xhci.h>
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/lpc.h>
+#include <soc/pattrs.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+#include <soc/ramstage.h>
+#include <soc/xhci.h>
 
 #include "chip.h"