summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorElyes HAOUAS <ehaouas@noos.fr>2019-05-22 20:26:02 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-06-03 13:29:08 +0000
commit19cb6c9980f86bb602c988f48dbf20413f2c27bf (patch)
treeed6d49fb1b3e38d935d8e257988ac483364cfb59 /src
parent9c8895fd889b01fe71bb296e2566b96a9542b303 (diff)
downloadcoreboot-19cb6c9980f86bb602c988f48dbf20413f2c27bf.tar.xz
sb/intel/fsp_rangeley: Remove variable set but not used
Change-Id: Ia2bc9bb0f0ece5ae3a57662b54f3e7e78ce00b19 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/intel/fsp_rangeley/romstage.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 19e470e309..2c2427eed1 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -90,7 +90,6 @@ void main(FSP_INFO_HEADER *fsp_info_header)
* Memory is setup and the stack is set by the FSP.
*/
void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
- int cbmem_was_initted;
void *cbmem_hob_ptr;
timestamp_add_now(TS_AFTER_INITRAM);
@@ -113,7 +112,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
/* Decode E0000 and F0000 segment to DRAM */
sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0));
- cbmem_was_initted = !cbmem_recovery(0);
+ cbmem_recovery(0);
/* Save the HOB pointer in CBMEM to be used in ramstage*/
cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr));