diff options
author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-11-24 14:11:47 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-01-24 23:20:02 +0100 |
commit | 19ce16ae69f31ef37c5edcbc3621a8060176b7e9 (patch) | |
tree | a2f93ed4236e62fb56b7baa4d65f31ff2cc01b57 /src | |
parent | a39e6d1cf90a2be7a5311625b5d6be85921e8977 (diff) | |
download | coreboot-19ce16ae69f31ef37c5edcbc3621a8060176b7e9.tar.xz |
northbridge/amd/amdfam10: Update DRAM speed limits for C32 sockets
The existing code applied G34-specific speed limits to all socket
types. Update G34 and C32 specific speed limits to be in line with
BKDG recommendations.
Change-Id: I958ad333c47948ae741a56de5866af3e636fd24d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13140
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/northbridge/amd/amdfam10/raminit_amdmct.c | 346 |
1 files changed, 259 insertions, 87 deletions
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index a40c5a1015..1407631e80 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -180,141 +180,313 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8 } if (is_fam15h()) { - if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { - /* Fam15h BKDG Rev. 3.14 Table 27 */ - if (voltage & 0x4) { - /* 1.25V */ - if (count > 1) { - if (highest_rank_count > 1) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); + if (CONFIG_CPU_SOCKET_TYPE == 0x15) { + /* Socket G34 */ + if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { + /* Fam15h BKDG Rev. 3.14 Table 27 */ + if (voltage & 0x4) { + /* 1.25V */ + if (count > 1) { + if (highest_rank_count > 1) { + /* Limit to DDR3-1066 */ + if (freq > 533) { + freq = 533; + printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); + } + } else { + /* Limit to DDR3-1333 */ + if (freq > 666) { + freq = 666; + printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); + } } } else { /* Limit to DDR3-1333 */ if (freq > 666) { freq = 666; + printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); + } + } + } else if (voltage & 0x2) { + /* 1.35V */ + if (count > 1) { + /* Limit to DDR3-1333 */ + if (freq > 666) { + freq = 666; printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); } + } else { + /* Limit to DDR3-1600 */ + if (freq > 800) { + freq = 800; + printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); + } } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); + } else if (voltage & 0x1) { + /* 1.50V */ + if (count > 1) { + /* Limit to DDR3-1600 */ + if (freq > 800) { + freq = 800; + printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); + } + } else { + /* Limit to DDR3-1866 */ + if (freq > 933) { + freq = 933; + printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage)); + } } } - } else if (voltage & 0x2) { - /* 1.35V */ - if (count > 1) { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); + } else { + /* Fam15h BKDG Rev. 3.14 Table 26 */ + if (voltage & 0x4) { + /* 1.25V */ + if (count > 1) { + if (highest_rank_count > 1) { + /* Limit to DDR3-1066 */ + if (freq > 533) { + freq = 533; + printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); + } + } else { + /* Limit to DDR3-1333 */ + if (freq > 666) { + freq = 666; + printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); + } + } + } else { + /* Limit to DDR3-1333 */ + if (freq > 666) { + freq = 666; + printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); + } } - } - } else if (voltage & 0x1) { - /* 1.50V */ - if (count > 1) { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); + } else if (voltage & 0x2) { + /* 1.35V */ + if (MaxDimmsInstallable > 1) { + /* Limit to DDR3-1333 */ + if (freq > 666) { + freq = 666; + printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); + } + } else { + /* Limit to DDR3-1600 */ + if (freq > 800) { + freq = 800; + printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); + } } - } else { - /* Limit to DDR3-1866 */ - if (freq > 933) { - freq = 933; - printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage)); + } else if (voltage & 0x1) { + if (MaxDimmsInstallable == 1) { + if (count > 1) { + /* Limit to DDR3-1600 */ + if (freq > 800) { + freq = 800; + printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); + } + } else { + /* Limit to DDR3-1866 */ + if (freq > 933) { + freq = 933; + printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage)); + } + } + } else { + if (count > 1) { + if (highest_rank_count > 1) { + /* Limit to DDR3-1333 */ + if (freq > 666) { + freq = 666; + printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); + } + } else { + /* Limit to DDR3-1600 */ + if (freq > 800) { + freq = 800; + printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); + } + } + } else { + /* Limit to DDR3-1600 */ + if (freq > 800) { + freq = 800; + printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); + } + } } } } - } else { - /* Fam15h BKDG Rev. 3.14 Table 26 */ - if (voltage & 0x4) { - /* 1.25V */ - if (count > 1) { - if (highest_rank_count > 1) { - /* Limit to DDR3-1066 */ - if (freq > 533) { - freq = 533; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); + } else if (CONFIG_CPU_SOCKET_TYPE == 0x14) { + /* Socket C32 */ + if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { + /* Fam15h BKDG Rev. 3.14 Table 30 */ + if (voltage & 0x4) { + /* 1.25V */ + if (count > 1) { + if (highest_rank_count > 2) { + /* Limit to DDR3-800 */ + if (freq > 400) { + freq = 400; + printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage)); + } + } else { + /* Limit to DDR3-1333 */ + if (freq > 666) { + freq = 666; + printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); + } } } else { /* Limit to DDR3-1333 */ if (freq > 666) { freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); + printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); } } - } else { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x2) { - /* 1.35V */ - if (MaxDimmsInstallable > 1) { - /* Limit to DDR3-1333 */ - if (freq > 666) { - freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1600 */ - if (freq > 800) { - freq = 800; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } - } else if (voltage & 0x1) { - if (MaxDimmsInstallable == 1) { + } else if (voltage & 0x2) { + /* 1.35V */ if (count > 1) { + if (highest_rank_count > 2) { + /* Limit to DDR3-800 */ + if (freq > 400) { + freq = 400; + printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage)); + } + } else if (highest_rank_count > 1) { + /* Limit to DDR3-1066 */ + if (freq > 533) { + freq = 533; + printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); + } + } else { + /* Limit to DDR3-1333 */ + if (freq > 666) { + freq = 666; + printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); + } + } + } else { /* Limit to DDR3-1600 */ if (freq > 800) { freq = 800; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); - } - } else { - /* Limit to DDR3-1866 */ - if (freq > 933) { - freq = 933; - printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage)); + printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); } } - } else { + } else if (voltage & 0x1) { + /* 1.50V */ if (count > 1) { - if (highest_rank_count > 1) { + if (highest_rank_count > 2) { + /* Limit to DDR3-800 */ + if (freq > 400) { + freq = 400; + printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage)); + } + } else if (highest_rank_count > 1) { + /* Limit to DDR3-1066 */ + if (freq > 533) { + freq = 533; + printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); + } + } else { /* Limit to DDR3-1333 */ if (freq > 666) { freq = 666; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); + printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); + } + } + } else { + if (highest_rank_count > 2) { + /* Limit to DDR3-1333 */ + if (freq > 666) { + freq = 666; + printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); } } else { /* Limit to DDR3-1600 */ if (freq > 800) { freq = 800; - printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); + printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); + } + } + } + } + } else { + /* Fam15h BKDG Rev. 3.14 Table 29 */ + if (voltage & 0x4) { + /* 1.25V */ + if (count > 1) { + /* Limit to DDR3-1066 */ + if (freq > 533) { + freq = 533; + printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); + } + } else { + /* Limit to DDR3-1333 */ + if (freq > 666) { + freq = 666; + printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); + } + } + } else if (voltage & 0x2) { + if (count > 1) { + if (highest_rank_count > 1) { + /* Limit to DDR3-1066 */ + if (freq > 533) { + freq = 533; + printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); + } + } else { + /* Limit to DDR3-1333 */ + if (freq > 666) { + freq = 666; + printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); } } } else { + /* Limit to DDR3-1333 */ + if (freq > 666) { + freq = 666; + printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); + } + } + } else if (voltage & 0x1) { + if (MaxDimmsInstallable == 1) { /* Limit to DDR3-1600 */ if (freq > 800) { freq = 800; printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); } + } else { + if (count > 1) { + if (highest_rank_count > 1) { + /* Limit to DDR3-1066 */ + if (freq > 533) { + freq = 533; + printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); + } + } else { + /* Limit to DDR3-1333 */ + if (freq > 666) { + freq = 666; + printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); + } + } + } else { + /* Limit to DDR3-1600 */ + if (freq > 800) { + freq = 800; + printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); + } + } } } } + } else { + /* TODO + * Other socket support unimplemented + */ } } else { if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { |