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authorAaron Durbin <adurbin@chromium.org>2014-01-09 11:17:37 -0600
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-05-13 16:11:25 +0200
commit19edc3a2e53eb54994a99ca8a868480badcbf227 (patch)
treec2c02125913d00ebf5aaddae673a3c4a18ab26a6 /src
parent8f31ecf28b9788d007be746fc85160cb6e91c1ca (diff)
downloadcoreboot-19edc3a2e53eb54994a99ca8a868480badcbf227.tar.xz
baytrail: clear the pmc wake status registers
The PMC in baytrail maintains an additional set wake status in memory-mapped registers. If these bits aren't cleared the device won't be able to go to S5 or S3 without being immediately woken up. Therefore clear these registers. BUG=chrome-os-partner:24913 BRANCH=rambi,squawks TEST=Ensured PRSTS bit 4 is cleared after a reboot and S3 and S5 work correctly. Change-Id: I356e00ece851961135b4760cebcdd34e8b9da027 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181984 Reviewed-on: http://review.coreboot.org/5034 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/baytrail/baytrail/pmc.h1
-rw-r--r--src/soc/intel/baytrail/pmutil.c14
-rw-r--r--src/soc/intel/baytrail/smm.c1
3 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/baytrail/pmc.h b/src/soc/intel/baytrail/baytrail/pmc.h
index 5013db8b08..ccbeed8770 100644
--- a/src/soc/intel/baytrail/baytrail/pmc.h
+++ b/src/soc/intel/baytrail/baytrail/pmc.h
@@ -270,6 +270,7 @@ uint16_t clear_pm1_status(void);
uint32_t clear_tco_status(void);
uint32_t clear_gpe_status(void);
uint32_t clear_alt_status(void);
+void clear_pmc_status(void);
void enable_smi(uint32_t mask);
void disable_smi(uint32_t mask);
void enable_pm1(uint16_t events);
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index ad37511534..5d37a1366d 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -21,6 +21,7 @@
#include <arch/io.h>
#include <console/console.h>
+#include <baytrail/iomap.h>
#include <baytrail/lpc.h>
#include <baytrail/pci_devs.h>
#include <baytrail/pmc.h>
@@ -348,3 +349,16 @@ uint32_t clear_alt_status(void)
{
return print_alt_sts(reset_alt_status());
}
+
+void clear_pmc_status(void)
+{
+ uint32_t prsts;
+ uint32_t gen_pmcon1;
+
+ prsts = read32(PMC_BASE_ADDRESS + PRSTS);
+ gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+
+ /* Clear the status bits. */
+ write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1);
+ write32(PMC_BASE_ADDRESS + PRSTS, prsts);
+}
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index e10c70b699..1fb35d7616 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -62,6 +62,7 @@ void southcluster_smm_clear_state(void)
clear_tco_status();
clear_gpe_status();
clear_alt_status();
+ clear_pmc_status();
}
static void southcluster_smm_route_gpios(void)