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authorMichael Niewöhner <foss@mniewoehner.de>2020-02-23 22:51:05 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-02-25 10:17:17 +0000
commit1c8e464e36f380046588476e50a382539aba4e23 (patch)
tree109a475ab20485f0aa121ca84aeb1bfdf4adffd0 /src
parent4311d9f8528360f0c161d511a016b643b68562f1 (diff)
downloadcoreboot-1c8e464e36f380046588476e50a382539aba4e23.tar.xz
mb/supermicro/x11-lga1151-series: fix PNP warning for SUART1/2
Fix PNP warning about missing devicetree entry for SUART1/2 by setting register 0xF0 to a sane (default) value. Change-Id: Ie852696aae09b9b03cebd6c3d8cbbd53a7138d89 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb2
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb2
2 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
index f481c77bda..074e61bfbc 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
@@ -100,10 +100,12 @@ chip soc/intel/skylake
device pnp 2e.2 on # SUART1
io 0x60 = 0x3f8
irq 0x70 = 4
+ drq 0xf0 = 0x00
end
device pnp 2e.3 on # SUART2
io 0x60 = 0x2f8
irq 0x70 = 3
+ drq 0xf0 = 0x00
end
device pnp 2e.4 on # SWC
io 0x60 = 0xa00
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
index 0c7c17fffe..76e684ce4d 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
@@ -87,10 +87,12 @@ chip soc/intel/skylake
device pnp 2e.2 on # SUART1 / COM1 (ext)
io 0x60 = 0x3f8
irq 0x70 = 4
+ drq 0xf0 = 0x00
end
device pnp 2e.3 on # SUART2 / COM2 (int)
io 0x60 = 0x2f8
irq 0x70 = 3
+ drq 0xf0 = 0x00
end
device pnp 2e.4 on # SWC
io 0x60 = 0xa00