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authorDuncan Laurie <dlaurie@google.com>2018-12-01 17:00:23 -0800
committerDuncan Laurie <dlaurie@chromium.org>2018-12-04 22:50:06 +0000
commit1e64d2386a5f281c294666cec59b45f37c40338d (patch)
tree92a9b50991550e8d94f21e556f1a2125666a6096 /src
parent11340e5e1e89011f914d7f3e87bd5d9b004b2587 (diff)
downloadcoreboot-1e64d2386a5f281c294666cec59b45f37c40338d.tar.xz
soc/intel/cannonlake: Add USB device names
Add the ACPI device names for the USB ports to match what is in the DSDT so USB ports can be defined in the SSDT. Change-Id: Ibb323bbd324811fa3178b0cba3d7f0a315169486 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/cannonlake/chip.c37
1 files changed, 37 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 17b173aec6..4604d80f1a 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -35,6 +35,43 @@ const char *soc_acpi_name(const struct device *dev)
if (dev->path.type == DEVICE_PATH_DOMAIN)
return "PCI0";
+ if (dev->path.type == DEVICE_PATH_USB) {
+ switch (dev->path.usb.port_type) {
+ case 0:
+ /* Root Hub */
+ return "RHUB";
+ case 2:
+ /* USB2 ports */
+ switch (dev->path.usb.port_id) {
+ case 0: return "HS01";
+ case 1: return "HS02";
+ case 2: return "HS03";
+ case 3: return "HS04";
+ case 4: return "HS05";
+ case 5: return "HS06";
+ case 6: return "HS07";
+ case 7: return "HS08";
+ case 8: return "HS09";
+ case 9: return "HS10";
+ case 10: return "HS11";
+ case 11: return "HS12";
+ }
+ break;
+ case 3:
+ /* USB3 ports */
+ switch (dev->path.usb.port_id) {
+ case 0: return "SS01";
+ case 1: return "SS02";
+ case 2: return "SS03";
+ case 3: return "SS04";
+ case 4: return "SS05";
+ case 5: return "SS06";
+ }
+ break;
+ }
+ return NULL;
+ }
+
if (dev->path.type != DEVICE_PATH_PCI)
return NULL;