summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2019-05-23 14:37:40 +0200
committerArthur Heymans <arthur@aheymans.xyz>2019-05-27 09:08:19 +0000
commit1f925b15ae65ae4789b2ae1dd2ef8b4bbdc4e9f1 (patch)
tree2a63daa4eadf7e7d9009f133e007d829fbe159c5 /src
parent7ae606f57f0b3d450ae748141b0e2367041b27d3 (diff)
downloadcoreboot-1f925b15ae65ae4789b2ae1dd2ef8b4bbdc4e9f1.tar.xz
drivers/intel/fsp1.1: Remove stale comment on bootflow
This list is incorrect and not up to date. The FSP1.1 romstage bootflow is unnecessarily clumsy and instead of trying to update this comment effort is better spend making the bootflow more streamlined. Change-Id: If1e4c462acd0748f072f33e6397a7b43f3bfc834 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src')
-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/romstage.h35
1 files changed, 0 insertions, 35 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index de37950887..6ddafd858b 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -42,41 +42,6 @@ struct romstage_params {
const void *data_to_save;
};
-/*
- * FSP Boot Flow:
- * 1. src/cpu/x86/16bit/reset.inc
- * 2. src/cpu/x86/16bit/entry.inc
- * 3. other modules
- * 4. src/drivers/intel/fsp1_1/cache_as_ram.inc
- * 5. src/drivers/intel/fsp1_1/fsp_util.c/find_fsp
- * 6. FSP binary/TempRamInit
- * 7. src/drivers/intel/fsp1_1/cache_as_ram.inc - return
- * 8. src/soc/intel/common/romstage.c/romstage_main
- * 9 src/soc/.../romstage/.../soc_pre_console_init
- * 10 src/console/console.c/console_init
- * 11 src/soc/.../romstage/.../soc_romstage_init
- * 12. src/mainboard/.../romstage.c/mainboard_romstage_entry
- * 13. src/soc/intel/common/romstage.c/romstage_common
- * 14 src/soc/.../romstage/.../soc_pre_raminit
- * 15. FSP binary/MemoryInit
- * 16. src/soc/intel/common/romstage.c/romstage_common - return
- * 17. src/mainboard/.../romstage.c/mainboard_romstage_entry - return
- * 18. src/soc/intel/common/romstage.c/romstage_main - return
- * 19. src/soc/intel/common/stack.c/setup_stack_and_mtrrs
- * 20. src/drivers/intel/fsp1_1/cache_as_ram.inc - return, cleanup
- * after call to romstage_main
- * 21. FSP binary/TempRamExit
- * 22. src/soc/intel/common/romstage.c/romstage_after_car
- * 23. FSP binary/SiliconInit
- * 24. src/soc/intel/common/romstage.c/romstage_after_car - return
- * 25. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback
- * 26. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify
- * 27. FSP binary/FspNotify
- * 28. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback
- * 29. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify
- * 30. FSP binary/FspNotify
- */
-
void mainboard_memory_init_params(struct romstage_params *params,
MEMORY_INIT_UPD *memory_params);
void mainboard_romstage_entry(struct romstage_params *params);