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authorPaul Menzel <paulepanter@users.sourceforge.net>2014-02-11 10:38:27 +0100
committerMarc Jones <marc.jones@se-eng.com>2014-02-24 21:58:08 +0100
commit20f83d56561879045ecade24d51e79dfb151baf6 (patch)
tree97b3491c07b9f8dc7628e9d94d28be55f6fd1e74 /src
parente3f75f8ecaf1aab1bee1f1f79caa35c526c124a5 (diff)
downloadcoreboot-20f83d56561879045ecade24d51e79dfb151baf6.tar.xz
intel/*/acpi: Increase range length of MCHBAR buffer to 32 kB
Linux kernel 2.6.31 reports the warning below on Intel Ivy Bridge (with FSP). resource map sanity check conflict: 0xfed10000 0xfed17fff 0xfed10000 0xfed13fff pnp 00:01 Since Sandy Bridge the length of the MCHBAR is 32 kB and it is already used that way in other places. $ more src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl […] OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) […] So instead of 16 kB specify that 32 kB are decoded in that memory range for Intel Sandy Bridge, Ivy Bridge and Haswell. (Linux kernel 3.10 does not warn about that.) Change-Id: Ie7a9356d9051c807833df85e4a806e5a9498473f Reported-by: Norwich in #coreboot on <irc.freenode.org> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5192 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Werner Zeh Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl2
-rw-r--r--src/northbridge/intel/haswell/acpi/haswell.asl2
-rw-r--r--src/northbridge/intel/nehalem/acpi/nehalem.asl2
-rw-r--r--src/northbridge/intel/sandybridge/acpi/sandybridge.asl2
4 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl
index 7d51135f44..e6012ffdfc 100644
--- a/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl
+++ b/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl
@@ -30,7 +30,7 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
- Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
+ Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl
index 1634fe3785..4db7295502 100644
--- a/src/northbridge/intel/haswell/acpi/haswell.asl
+++ b/src/northbridge/intel/haswell/acpi/haswell.asl
@@ -30,7 +30,7 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
- Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
+ Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/nehalem/acpi/nehalem.asl
index aa74d0db34..3c6c2388fd 100644
--- a/src/northbridge/intel/nehalem/acpi/nehalem.asl
+++ b/src/northbridge/intel/nehalem/acpi/nehalem.asl
@@ -30,7 +30,7 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
- Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
+ Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
index 6708e270e9..e32d5f18fc 100644
--- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
@@ -30,7 +30,7 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
- Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
+ Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)