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authorJulius Werner <jwerner@chromium.org>2019-11-13 11:28:27 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-11-14 17:10:13 +0000
commit211792feaba4a5cc26b4e3f17e905c3e899eb07f (patch)
tree328680149ddf7cc17902b04d7efb99a2688d2d86 /src
parentdd0dc1ac9234fd2d6e786146739172eba0d4564f (diff)
downloadcoreboot-211792feaba4a5cc26b4e3f17e905c3e899eb07f.tar.xz
rockchip/rk3288: Split free SRAM more evenly between stages
When CB:33068 disabled the bootblock console on RK3288, it saved a whooping 7K of SRAM, but it didn't readjust the stage boundaries to spread that bounty evenly. This patch moves 4K of free space from the bootblock to verstage/romstage to allow for future expansion. Change-Id: I68a09ba80bde0d4f17fba1f7b38c63b7cf2a4672 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/rockchip/rk3288/include/soc/memlayout.ld8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 94a672db0c..f8e186c9d6 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -30,10 +30,10 @@ SECTIONS
SRAM_START(0xFF700000)
TTB(0xFF700000, 16K)
- BOOTBLOCK(0xFF704004, 20K - 4)
- PRERAM_CBMEM_CONSOLE(0xFF709000, 2K)
- VBOOT2_WORK(0xFF709800, 12K)
- OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 42K + 768)
+ BOOTBLOCK(0xFF704004, 16K - 4)
+ PRERAM_CBMEM_CONSOLE(0xFF708000, 2K)
+ VBOOT2_WORK(0xFF708800, 12K)
+ OVERLAP_VERSTAGE_ROMSTAGE(0xFF70B800, 46K + 768)
PRERAM_CBFS_CACHE(0xFF717300, 256)
TIMESTAMP(0xFF717400, 0x180)
STACK(0xFF717580, 3K - 0x180)