Move CS5535 specific setup from GX2 driver to CS5535.

To apply this patch you need to 
cp src/northbridge/amd/gx2/chipsetinit.c src/southbridge/amd/cs5535/

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Nils Jacobs <njacobs8@hetnet.nl>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

13 files changed, 43 insertions, 68 deletions

diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb
index ac4f4b494d..7ccb1fcf97 100644
--- a/src/mainboard/amd/rumba/devicetree.cb
+++ b/src/mainboard/amd/rumba/devicetree.cb
@@ -1,5 +1,4 @@
 chip northbridge/amd/gx2
-	register "setupflash" = "0"
   	#register "irqmap" = "0xaa5b"
 	device lapic_cluster 0 on
 		chip cpu/amd/model_gx2
diff --git a/src/mainboard/lippert/frontrunner/devicetree.cb b/src/mainboard/lippert/frontrunner/devicetree.cb
index 1386de9d77..9c1807629b 100644
--- a/src/mainboard/lippert/frontrunner/devicetree.cb
+++ b/src/mainboard/lippert/frontrunner/devicetree.cb
@@ -1,9 +1,15 @@
 chip northbridge/amd/gx2
-  register "setupflash" = "0"
+  device lapic_cluster 0 on
+    chip cpu/amd/model_gx2
+      device lapic 0 on end
+    end
+  end
+
   #register "irqmap" = "0xaa5b"
   device pci_domain 0 on
     device pci 0.0 on end
       chip southbridge/amd/cs5535
+  	register "setupflash" = "0"
         device pci 12.0 on
         device pci 12.1 off end		# SMI
         device pci 12.2 on  end		# IDE
@@ -12,9 +18,5 @@ chip northbridge/amd/gx2
       end
     end
   end
-
-  chip cpu/amd/model_gx2
-  end
-
 end
 
diff --git a/src/mainboard/olpc/btest/devicetree.cb b/src/mainboard/olpc/btest/devicetree.cb
index 3dfe710833..6fec1f0184 100644
--- a/src/mainboard/olpc/btest/devicetree.cb
+++ b/src/mainboard/olpc/btest/devicetree.cb
@@ -1,6 +1,5 @@
 chip northbridge/amd/gx2
 	register "irqmap" = "0xaa5b"
-	register "setupflash" = "0"
 	device lapic_cluster 0 on
 		chip cpu/amd/model_gx2
 			device lapic 0 on end
diff --git a/src/mainboard/olpc/rev_a/devicetree.cb b/src/mainboard/olpc/rev_a/devicetree.cb
index 3dfe710833..6fec1f0184 100644
--- a/src/mainboard/olpc/rev_a/devicetree.cb
+++ b/src/mainboard/olpc/rev_a/devicetree.cb
@@ -1,6 +1,5 @@
 chip northbridge/amd/gx2
 	register "irqmap" = "0xaa5b"
-	register "setupflash" = "0"
 	device lapic_cluster 0 on
 		chip cpu/amd/model_gx2
 			device lapic 0 on end
diff --git a/src/mainboard/wyse/s50/devicetree.cb b/src/mainboard/wyse/s50/devicetree.cb
index 2c48e74dfb..b88bc46b12 100644
--- a/src/mainboard/wyse/s50/devicetree.cb
+++ b/src/mainboard/wyse/s50/devicetree.cb
@@ -21,7 +21,7 @@
 
 chip northbridge/amd/gx2
 	register "irqmap" = "0xaa5b"
-	register "setupflash" = "0"
+
 	device lapic_cluster 0 on
 		chip cpu/amd/model_gx2
 			device lapic 0 on end
diff --git a/src/northbridge/amd/gx2/Makefile.inc b/src/northbridge/amd/gx2/Makefile.inc
index eb8a5dbc2d..f86105fd2e 100644
--- a/src/northbridge/amd/gx2/Makefile.inc
+++ b/src/northbridge/amd/gx2/Makefile.inc
@@ -1,4 +1,3 @@
 driver-y += northbridge.o
 obj-y += northbridgeinit.o
-obj-y += chipsetinit.o
 obj-y += grphinit.o
diff --git a/src/northbridge/amd/gx2/chip.h b/src/northbridge/amd/gx2/chip.h
index 556c0e1de0..60b5691c29 100644
--- a/src/northbridge/amd/gx2/chip.h
+++ b/src/northbridge/amd/gx2/chip.h
@@ -1,7 +1,6 @@
 struct northbridge_amd_gx2_config
 {
  	uint16_t irqmap;
-	int setupflash;
 };
 
 extern struct chip_operations northbridge_amd_gx2_ops;
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index 42fdcbb496..bb41fd057d 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -486,13 +486,12 @@ static void enable_dev(struct device *dev)
 
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
-		struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
 		u32 tomk;
 		printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n");
 		/* cpubug MUST be called before setup_gx2(), so we force the issue here */
 		northbridgeinit();
 		cpubug();
-		gx2_chipsetinit(nb);
+		chipsetinit();
 		setup_gx2();
 		do_vsmbios();
 		graphics_init();
diff --git a/src/northbridge/amd/gx2/northbridge.h b/src/northbridge/amd/gx2/northbridge.h
index cd3af80cd5..f42ff6aa47 100644
--- a/src/northbridge/amd/gx2/northbridge.h
+++ b/src/northbridge/amd/gx2/northbridge.h
@@ -6,7 +6,6 @@
 #else
 unsigned int gx2_scan_root_bus(device_t root, unsigned int max);
 int sizeram(void);
-void gx2_chipsetinit (struct northbridge_amd_gx2_config *nb);
 void graphics_init(void);
 void northbridgeinit(void);
 #endif
diff --git a/src/southbridge/amd/cs5535/Makefile.inc b/src/southbridge/amd/cs5535/Makefile.inc
index aab992fb89..8af55640f3 100644
--- a/src/southbridge/amd/cs5535/Makefile.inc
+++ b/src/southbridge/amd/cs5535/Makefile.inc
@@ -1,3 +1,4 @@
 driver-y += cs5535.o
 #driver-y += cs5535_pci.o
 #driver-y += cs5535_ide.o
+obj-y += chipsetinit.o
diff --git a/src/southbridge/amd/cs5535/chip.h b/src/southbridge/amd/cs5535/chip.h
index 1a02d59e8e..3894a06906 100644
--- a/src/southbridge/amd/cs5535/chip.h
+++ b/src/southbridge/amd/cs5535/chip.h
@@ -4,7 +4,7 @@
 extern struct chip_operations southbridge_amd_cs5535_ops;
 
 struct southbridge_amd_cs5535_config {
-	int none;
+	int setupflash;
 };
 
 #endif	/* _SOUTHBRIDGE_AMD_CS5536 */
diff --git a/src/northbridge/amd/gx2/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c
index 1d0edc4c4d..d31efd3e52 100644
--- a/src/northbridge/amd/gx2/chipsetinit.c
+++ b/src/southbridge/amd/cs5535/chipsetinit.c
@@ -8,10 +8,12 @@
 #include <string.h>
 #include <bitops.h>
 #include "chip.h"
-#include "northbridge.h"
+#include "northbridge/amd/gx2/northbridge.h"
 #include <cpu/amd/gx2def.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/cache.h>
+#include "southbridge/amd/cs5535/cs5535.h"
+// This code uses some cs5536 includes because cs5535 includes are empty:
 #include "southbridge/amd/cs5536/cs5536.h"
 
 /* the structs in this file only set msr.lo. But ... that may not always be true */
@@ -47,18 +49,6 @@ static struct msrinit CS5535_CLOCK_GATING_TABLE[] = {
 	{ 0,			{.hi=0, .lo=0x000000000} }
 };
 
-/*  5536 Clock Gating*/
-static struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
-/* MSR		  Setting*/
-	{ GLIU_SB_GLD_MSR_PM,	{.hi=0, .lo=0x000000004} },
-	{ GLPCI_SB_GLD_MSR_PM,	{.hi=0, .lo=0x000000005} },
-	{ GLCP_SB_GLD_MSR_PM,	{.hi=0, .lo=0x000000004} },
-	{ MDD_SB_GLD_MSR_PM,	{.hi=0, .lo=0x050554111} }, /*  SMBus clock gating errata (PBZ 2226 & SiBZ 3977) */
-	{ ATA_SB_GLD_MSR_PM,	{.hi=0, .lo=0x000000005} },
-	{ AC97_SB_GLD_MSR_PM,	{.hi=0, .lo=0x000000005} },
-	{ 0,			{.hi=0, .lo=0x000000000} }
-};
-
 #ifdef UNUSED_CODE
 struct acpiinit {
 	unsigned short ioreg;
@@ -81,19 +71,7 @@ static struct acpiinit acpi_init_table[] = {
 	{PM_WKXD, 0x0000000A0, 4},
 	{0,0,0}
 };
-#endif
 
-/* return 1 if we are a 5536-based system */
-static int is_5536(void)
-{
-	msr_t msr;
-	msr = rdmsr(GLIU_SB_GLD_MSR_CAP);
-	msr.lo >>= 20;
-	printk(BIOS_DEBUG, "is_5536: msr.lo is 0x%x(==5 means 5536)\n", msr.lo&0xf);
-	return ((msr.lo&0xf) == 5);
-}
-
-#ifdef UNUSED_CODE
 /*****************************************************************************
  *
  *	pmChipsetInit
@@ -256,9 +234,6 @@ ChipsetGeodeLinkInit(void)
 	unsigned long msrnum;
 	unsigned long totalmem;
 
-	if (is_5536())
-		return;
-
 	/*  SWASIF for A1 DMA */
 	/*  Set all memory to  "just above systop" PCI so DMA will work */
 
@@ -279,18 +254,33 @@ ChipsetGeodeLinkInit(void)
 }
 
 void
-gx2_chipsetinit (struct northbridge_amd_gx2_config *nb)
+chipsetinit(void)
 {
+	device_t dev;
+	struct southbridge_amd_cs5535_config *sb;
 	msr_t msr;
 	struct msrinit *csi;
 	int i;
 	unsigned long msrnum;
 
+	dev = dev_find_device(PCI_VENDOR_ID_AMD,
+			PCI_DEVICE_ID_NS_CS5535_ISA, 0);
+
+	if (!dev) {
+		printk(BIOS_ERR, "CS5535 not found.\n");
+		return;
+	}
+
+	sb = (struct southbridge_amd_cs5535_config *)dev->chip_info;
+
+	if (!sb) {
+		printk(BIOS_ERR, "CS5535 configuration not found.\n");
+		return;
+	}
+
 	outb( P80_CHIPSET_INIT, 0x80);
 	ChipsetGeodeLinkInit();
 
-	printk(BIOS_DEBUG, "Companion is a %s\n", is_5536()?"CS5536":"CS5535");
-
 #ifdef UNUSED_CODE
 	/* we hope NEVER to be in coreboot when S3 resumes
 	if (! IsS3Resume()) */
@@ -310,15 +300,13 @@ gx2_chipsetinit (struct northbridge_amd_gx2_config *nb)
 	}
 #endif
 
-	if (!is_5536()) {
-		/*  Setup USB. Need more details. #118.18 */
-		msrnum = MSR_SB_USB1 + 8;
-		msr.lo =  0x00012090;
-		msr.hi = 0;
-		wrmsr(msrnum, msr);
-		msrnum = MSR_SB_USB2 + 8;
-		wrmsr(msrnum, msr);
-	}
+	/*  Setup USB. Need more details. #118.18 */
+	msrnum = MSR_SB_USB1 + 8;
+	msr.lo =  0x00012090;
+	msr.hi = 0;
+	wrmsr(msrnum, msr);
+	msrnum = MSR_SB_USB2 + 8;
+	wrmsr(msrnum, msr);
 
 	/* set hd IRQ */
 	outl	(GPIOL_2_SET, GPIOL_INPUT_ENABLE);
@@ -340,10 +328,7 @@ gx2_chipsetinit (struct northbridge_amd_gx2_config *nb)
 
 	/*  Set up Master Configuration Register */
 	/*  If 5536, use same master config settings as 5535, except for OHCI MSRs */
-	if (is_5536())
-		i = 2;
-	else
-		i = 0;
+	i = 0;
 
 	csi = &SB_MASTER_CONF_TABLE[i];
 	for(; csi->msrnum; csi++){
@@ -354,19 +339,16 @@ gx2_chipsetinit (struct northbridge_amd_gx2_config *nb)
 
 	/*  Flash Setup */
 	printk(BIOS_INFO, "%sDOING ChipsetFlashSetup()!\n",
-			nb->setupflash ? "" : "NOT ");
+			sb->setupflash ? "" : "NOT ");
 
-	if (nb->setupflash)
+	if (sb->setupflash)
 		ChipsetFlashSetup();
 
 	/*  Set up Hardware Clock Gating */
 
 	/* if (getnvram(TOKEN_SB_CLK_GATE) != TVALUE_DISABLE) */
 	{
-		if (is_5536())
-			csi = CS5536_CLOCK_GATING_TABLE;
-		else
-			csi = CS5535_CLOCK_GATING_TABLE;
+		csi = CS5535_CLOCK_GATING_TABLE;
 
 		for(; csi->msrnum; csi++){
 			msr.lo = csi->msr.lo;
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index dbf42b913f..29747db215 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -518,9 +518,6 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
  *
  *	Called from northbridge init (Pre-VSA).
  *
- *	NOTE! This function is NOT called if the CS5536 is combined with
- *	an AMD Geode GX2. It's ONLY used on Geode LX based systems.
- *
  ****************************************************************************/
 void chipsetinit(void)
 {