summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorElyes HAOUAS <ehaouas@noos.fr>2017-11-23 21:23:44 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2017-11-30 17:21:17 +0000
commit242ea84b017b7f2812a4a1ba4b4996e5f1bb35ab (patch)
treebd104e859220d84d30f56c3acb689ff7e0ca17b9 /src
parent3df9dbe8864adf6d41df2fe617c8818d1bad9d42 (diff)
downloadcoreboot-242ea84b017b7f2812a4a1ba4b4996e5f1bb35ab.tar.xz
intel: Replace msr(0x198) with msr(IA32_PERF_STATUS)
Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/22585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/model_6ex/model_6ex_init.c2
-rw-r--r--src/cpu/intel/model_6fx/model_6fx_init.c2
-rw-r--r--src/cpu/intel/speedstep/speedstep.c6
-rw-r--r--src/include/cpu/intel/speedstep.h2
-rw-r--r--src/mainboard/intel/eagleheights/romstage.c2
-rw-r--r--src/mainboard/intel/mtarvon/romstage.c2
-rw-r--r--src/northbridge/intel/i945/udelay.c2
7 files changed, 9 insertions, 9 deletions
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 6e5b339444..96830c495d 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -86,7 +86,7 @@ static void configure_misc(void)
wrmsr(IA32_MISC_ENABLE, msr);
// set maximum CPU speed
- msr = rdmsr(IA32_PERF_STS);
+ msr = rdmsr(IA32_PERF_STATUS);
int busratio_max = (msr.hi >> (40-32)) & 0x1f;
msr = rdmsr(IA32_PLATFORM_ID);
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index b5a68ccadf..a1433f6de1 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -94,7 +94,7 @@ static void configure_misc(void)
wrmsr(IA32_MISC_ENABLE, msr);
// set maximum CPU speed
- msr = rdmsr(IA32_PERF_STS);
+ msr = rdmsr(IA32_PERF_STATUS);
int busratio_max = (msr.hi >> (40-32)) & 0x1f;
msr = rdmsr(IA32_PLATFORM_ID);
diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c
index 96ac8e59e0..441f2a36af 100644
--- a/src/cpu/intel/speedstep/speedstep.c
+++ b/src/cpu/intel/speedstep/speedstep.c
@@ -55,15 +55,15 @@ static void speedstep_get_limits(sst_params_t *const params)
/* Read normal maximum parameters. */
/* Newer CPUs provide the normal maximum settings in
- IA32_PLATFORM_ID. The values in IA32_PERF_STS change
+ IA32_PLATFORM_ID. The values in IA32_PERF_STATUS change
when using turbo mode. */
msr = rdmsr(IA32_PLATFORM_ID);
params->max = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask);
if (cpu_id == 0x006e) {
/* Looks like Yonah CPUs don't have the frequency ratio in
- IA32_PLATFORM_ID. Use IA32_PERF_STS instead, the reading
+ IA32_PLATFORM_ID. Use IA32_PERF_STATUS instead, the reading
should be reliable as those CPUs don't have turbo mode. */
- msr = rdmsr(IA32_PERF_STS);
+ msr = rdmsr(IA32_PERF_STATUS);
params->max.ratio = (msr.hi & SPEEDSTEP_RATIO_VALUE_MASK)
>> SPEEDSTEP_RATIO_SHIFT;
}
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index 40234d5fca..59336ed0c6 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -36,7 +36,7 @@
/* Speedstep related MSRs */
#define IA32_PLATFORM_ID 0x017
-#define IA32_PERF_STS 0x198
+#define IA32_PERF_STATUS 0x198
#define IA32_PERF_CTL 0x199
#define MSR_THERM2_CTL 0x19D
#define IA32_MISC_ENABLES 0x1A0
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index c254f17b7e..21313eb491 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -171,7 +171,7 @@ void mainboard_romstage_entry(unsigned long bist)
* bits 47:32, where BUS_RATIO_MAX and VID_MAX
* are encoded
*/
- msr = rdmsr(IA32_PERF_STS);
+ msr = rdmsr(IA32_PERF_STATUS);
perf = msr.hi & 0x0000ffff;
/* Write VID_MAX & BUS_RATIO_MAX to
diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index cb3e870043..13f425e1cf 100644
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -100,7 +100,7 @@ void mainboard_romstage_entry(unsigned long bist)
/* Set CPU frequency/voltage to maximum */
/* FIXME: move to Pentium M init code */
- msr = rdmsr(0x198);
+ msr = rdmsr(IA32_PERF_STATUS);
perf = msr.hi & 0xffff;
msr = rdmsr(0x199);
msr.lo &= 0xffff0000;
diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
index 90f2638251..8447453435 100644
--- a/src/northbridge/intel/i945/udelay.c
+++ b/src/northbridge/intel/i945/udelay.c
@@ -56,7 +56,7 @@ void udelay(u32 us)
break;
}
- msr = rdmsr(0x198);
+ msr = rdmsr(IA32_PERF_STATUS);
divisor = (msr.hi >> 8) & 0x1f;
d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */