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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-14 16:36:09 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-20 07:17:40 +0100 |
| commit | 24e31e28c4df0cde4a35ccbed50e21e7da466ad6 (patch) | |
| tree | 03d10243fc0a919a752676f4df8847b43170157e /src | |
| parent | af87020f0a3a813e03d3b059ae4284bbc8848ff1 (diff) | |
| download | coreboot-24e31e28c4df0cde4a35ccbed50e21e7da466ad6.tar.xz | |
AGESA fam14: Increase MMCONF region
Increase to max 64 buses, as there are no benefits of limit 16.
NOTE: It appears there is no matching (early) programming of the
region to non-posted MMIO.
Change-Id: I664789f7bd90992840e5817555cd3621c2d1e86c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7813
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/amd/agesa/family14/Kconfig | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family14/agesawrapper.c | 17 |
2 files changed, 2 insertions, 17 deletions
diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index fef4b0aecf..3e73e5a78e 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -37,6 +37,6 @@ config MMCONF_BASE_ADDRESS config MMCONF_BUS_NUMBER int - default 16 + default 64 endif # NORTHBRIDGE_AMD_AGESA_FAMILY14 diff --git a/src/northbridge/amd/agesa/family14/agesawrapper.c b/src/northbridge/amd/agesa/family14/agesawrapper.c index 70d8918dec..fecec93cd3 100644 --- a/src/northbridge/amd/agesa/family14/agesawrapper.c +++ b/src/northbridge/amd/agesa/family14/agesawrapper.c @@ -34,8 +34,6 @@ #define FILECODE UNASSIGNED_FILE_FILECODE -#define MMCONF_ENABLE 1 - /* Define AMD Ontario APPU SSID/SVID */ #define AMD_APU_SVID 0x1022 #define AMD_APU_SSID 0x1234 @@ -102,24 +100,11 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID) PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; - UINT8 BusRangeVal = 0; - UINT8 BusNum; - UINT8 Index; - /* Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Address MSR register. */ - - for (Index = 0; Index < 8; Index++) { - BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; - if (BusNum == 1) { - BusRangeVal = Index; - break; - } - } - - MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64) (BusRangeVal << 2) | MMCONF_ENABLE); + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); /* |