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authorGreg Watson <jarrah@users.sourceforge.net>2003-11-09 23:26:56 +0000
committerGreg Watson <jarrah@users.sourceforge.net>2003-11-09 23:26:56 +0000
commit2f726c3e83da564b90f72b97cede8458c148f0ed (patch)
tree20804651fe4c4225a044733f0f1f32bc27d39db7 /src
parent33ddaac6fda0b114f95b6fefc13e08639a7d0e19 (diff)
downloadcoreboot-2f726c3e83da564b90f72b97cede8458c148f0ed.tar.xz
updated for v2
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/cpu/ppc/mpc74xx/Config.lb16
-rw-r--r--src/cpu/ppc/mpc74xx/mpc74xx.inc12
2 files changed, 15 insertions, 13 deletions
diff --git a/src/cpu/ppc/mpc74xx/Config.lb b/src/cpu/ppc/mpc74xx/Config.lb
index 34e1040596..ad0d5ac671 100644
--- a/src/cpu/ppc/mpc74xx/Config.lb
+++ b/src/cpu/ppc/mpc74xx/Config.lb
@@ -1,7 +1,21 @@
##
## CPU initialization
##
-initinclude "EARLY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc
+uses _RAMBASE
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+##
+## Use cache ram for initial setup
+##
+default USE_DCACHE_RAM=1
+## Set dcache ram above linuxbios image
+default DCACHE_RAM_BASE=_RAMBASE+0x100000
+## Dcache size is 16Kb
+default DCACHE_RAM_SIZE=16384
+
+initinclude "FAMILY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc
object clock.o
+initobject clock.o
diff --git a/src/cpu/ppc/mpc74xx/mpc74xx.inc b/src/cpu/ppc/mpc74xx/mpc74xx.inc
index 6d23c3ad7e..5f6cee20dc 100644
--- a/src/cpu/ppc/mpc74xx/mpc74xx.inc
+++ b/src/cpu/ppc/mpc74xx/mpc74xx.inc
@@ -89,13 +89,6 @@
mtsr 15, r0
isync
- /*
- * Initialize northbridge. This has to happen early because it
- * resets memory. Memory is on at this point, albeit with
- * pessimistic settings. We reconfigure later using I2C.
- */
- bl bsp_init_northbridge
-
/*
* Set up DBATs
*
@@ -183,8 +176,3 @@ tlblp:
ori r2, r2, HID0_ICE | HID0_ICFI
isync
mtspr HID0, r2
-
- /*
- * Must branch to start_payload once CPU initialization is completed
- */
- b start_payload