diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2019-12-16 16:51:38 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-19 17:48:15 +0000 |
| commit | 3280b7672907cd70609f90010a653fa47b4e7c85 (patch) | |
| tree | 28f2ea177a29fe6d62c04c2cec3ec38180f0a760 /src | |
| parent | 25eb1b3149ccb3f1f0599b9bc05c5b5f196d303d (diff) | |
| download | coreboot-3280b7672907cd70609f90010a653fa47b4e7c85.tar.xz | |
storage/mmc: Fix wrong frequency setting for HS speed mode
Emmc spec, JEDEC Standard No. 84-B51, section 6.6.2.3, selection
flow of HS400 using Enhanced Strobe states that host should change
frequency to ≤ 52MHz when switching to HS speed mode first. In
current code, mmc_select_hs400() calls mmc_select_hs() to do this,
however caps are not cleared, so when switching from HS200 to HS400,
caps will still have DRVR_CAP_HS200, and mmc_recalculate_clock() will
set 200Mhz instead of ≤ 52MHz. As a result, switching to HS400 will
intermittently fail.
BUG=b:140124451
TEST=Switch speed from HS200 to HS400 on WHL RVP.
Change-Id: Ie639c7616105cca638417d7bc1db95b561afb7af
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37775
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/commonlib/storage/mmc.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/commonlib/storage/mmc.c b/src/commonlib/storage/mmc.c index 0b682adc89..1e0f7d20f0 100644 --- a/src/commonlib/storage/mmc.c +++ b/src/commonlib/storage/mmc.c @@ -186,6 +186,7 @@ static int mmc_select_hs(struct storage_media *media) /* Increase the controller clock speed */ SET_TIMING(media->ctrlr, BUS_TIMING_MMC_HS); + media->caps &= ~(DRVR_CAP_HS200 | DRVR_CAP_HS400); media->caps |= DRVR_CAP_HS52 | DRVR_CAP_HS; mmc_recalculate_clock(media); ret = sd_mmc_send_status(media, SD_MMC_IO_RETRIES); |