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authorLijian Zhao <lijian.zhao@intel.com>2018-12-06 14:16:31 -0800
committerPatrick Georgi <pgeorgi@google.com>2018-12-11 08:59:13 +0000
commit331dfaff7087a97e48d4ac923d148f9dea3b09fb (patch)
tree3f2dc11a89ca6da00f7d7c5d2eaada68b8aa13da /src
parent2d92b1a3b1f2f42f36e035163b4658d440a082e1 (diff)
downloadcoreboot-331dfaff7087a97e48d4ac923d148f9dea3b09fb.tar.xz
mb/google/sarien: Disable unused SATA ports
Disable SATA port 0 and port 1 as that's not used as SATA on platform. BUG=N/A TEST=Build and boot up fine on google arcada board. Change-Id: I1b8801f7a0f9b7847b85d7c315fa0a2093b32f70 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 924f51d17f..ed2c34cbfe 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -18,11 +18,7 @@ chip soc/intel/cannonlake
register "HeciEnabled" = "1"
register "SataSalpSupport" = "1"
register "SataMode" = "0"
- register "SataPortsEnable[0]" = "0"
- register "SataPortsEnable[1]" = "1"
register "SataPortsEnable[2]" = "1"
- register "SataPortsDevSlp[0]" = "0"
- register "SataPortsDevSlp[1]" = "1"
register "SataPortsDevSlp[2]" = "1"
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"