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authorMichael Niewöhner <foss@mniewoehner.de>2019-10-19 21:15:15 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-10-22 12:35:17 +0000
commit33533c0e85899ea2d48aac539d67087b36cece63 (patch)
treebcefa453d29ccfee6ec0e143f2d1d6ab2a9780af /src
parente3aa424a4f53b8ac4c658a3cf33b7b52971599b3 (diff)
downloadcoreboot-33533c0e85899ea2d48aac539d67087b36cece63.tar.xz
mb/supermicro/x11-lga1151-series/x11ssh-tf: move usb to overridetree
Move USB ports from the common devicetree to the variants' overridetree as they differ at least for X11SSH-TF and X11SSM-F. Change-Id: I9bee3a8f6185296cadcee013a8dbe8dca256bf0b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/devicetree.cb64
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb36
2 files changed, 65 insertions, 35 deletions
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
index ee6aac7e17..b94bee8d90 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
@@ -59,41 +59,35 @@ chip soc/intel/skylake
# superspeed_inter-chip_supplement (SSIC) disabled
register "SsicPortEnable" = "0"
- # USB configuration
- # USB2/3
- register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
- register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
-
- # ?
- register "usb2_ports[14]" = "USB2_PORT_MID(OC0)"
- register "usb2_ports[15]" = "USB2_PORT_MID(OC0)"
-
- # USB4/5
- register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"
- register "usb2_ports[3]" = "USB2_PORT_MID(OC1)"
-
- # USB0/1
- register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
- register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
-
- # USB9/10 (USB3.0)
- register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"
- register "usb2_ports[12]" = "USB2_PORT_MID(OC3)"
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
- register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)"
-
- # USB6/7 (USB3.0)
- register "usb2_ports[10]" = "USB2_PORT_MID(OC4)"
- register "usb2_ports[11]" = "USB2_PORT_MID(OC4)"
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)"
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)"
-
- # USB8 (USB3.0)
- register "usb2_ports[9]" = "USB2_PORT_MID(OC5)"
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)"
-
- # IPMI USB HUB
- register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
+ # USB
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_EMPTY,
+ [1] = USB2_PORT_EMPTY,
+ [2] = USB2_PORT_EMPTY,
+ [3] = USB2_PORT_EMPTY,
+ [4] = USB2_PORT_EMPTY,
+ [5] = USB2_PORT_EMPTY,
+ [6] = USB2_PORT_EMPTY,
+ [7] = USB2_PORT_EMPTY,
+ [8] = USB2_PORT_EMPTY,
+ [9] = USB2_PORT_EMPTY,
+ [10] = USB2_PORT_EMPTY,
+ [11] = USB2_PORT_EMPTY,
+ [12] = USB2_PORT_EMPTY,
+ [13] = USB2_PORT_EMPTY,
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_EMPTY,
+ [1] = USB3_PORT_EMPTY,
+ [2] = USB3_PORT_EMPTY,
+ [3] = USB3_PORT_EMPTY,
+ [4] = USB3_PORT_EMPTY,
+ [5] = USB3_PORT_EMPTY,
+ [6] = USB3_PORT_EMPTY,
+ [7] = USB3_PORT_EMPTY,
+ [8] = USB3_PORT_EMPTY,
+ [9] = USB3_PORT_EMPTY,
+ }"
# LPC
register "serirq_mode" = "SERIRQ_CONTINUOUS"
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
index 09aa8b558c..3e587dc817 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
@@ -33,6 +33,42 @@ chip soc/intel/skylake
# FIXME: find out why FSP crashes without this
register "PchHdaVcType" = "Vc1"
+ # USB configuration
+ # USB2/3
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
+
+ # ?
+ register "usb2_ports[14]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[15]" = "USB2_PORT_MID(OC0)"
+
+ # USB4/5
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC1)"
+
+ # USB0/1
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
+
+ # USB9/10 (USB3.0)
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"
+ register "usb2_ports[12]" = "USB2_PORT_MID(OC3)"
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)"
+
+ # USB6/7 (USB3.0)
+ register "usb2_ports[10]" = "USB2_PORT_MID(OC4)"
+ register "usb2_ports[11]" = "USB2_PORT_MID(OC4)"
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)"
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)"
+
+ # USB8 (USB3.0)
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC5)"
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)"
+
+ # IPMI USB HUB
+ register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
+
device domain 0 on
device pci 01.0 on end # unused
device pci 01.1 on # PCIE Slot (JPCIE1)