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| author | Furquan Shaikh <furquan@google.com> | 2014-11-10 22:35:04 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-10 20:42:35 +0200 |
| commit | 3373ee6246d76ed6e0ff6083420ec8271eb035b1 (patch) | |
| tree | dbe6f3f01441d1bcc3c1eeef9cb9390b28a827ec /src | |
| parent | d0daebafde0b41275ab421585e4754c729848afe (diff) | |
| download | coreboot-3373ee6246d76ed6e0ff6083420ec8271eb035b1.tar.xz | |
tegra132: Increase space for romstage in memlayout
Stack and Timestamp need lesser than 2K and since romstage is running out of
memory, adjust the overall memory assignment.
BUG=chrome-os-partner:33676
BRANCH=None
TEST=Compiles and boots to kernel prompt.
Change-Id: I5076252ae87268bd4e964c282d1cc337e0ea4e70
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f2d5d29e6f0f5058a41ed30aae98f79574e31609
Original-Change-Id: I0134f25dd49f2940bb159d131aaee12f81e13ef7
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229001
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Tom Warren <twarren@nvidia.com>
Reviewed-on: http://review.coreboot.org/9512
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld index 1709392d13..c75bdc05bd 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -35,10 +35,10 @@ SECTIONS PRERAM_CBMEM_CONSOLE(0x40000000, 8K) CBFS_CACHE(0x40002000, 72K) VBOOT2_WORK(0x40014000, 16K) - STACK(0x40018000, 8K) - BOOTBLOCK(0x4001A000, 20K) - VERSTAGE(0x4001F000, 60K) - ROMSTAGE(0x4002E000, 72K) + STACK(0x40018000, 2K) + BOOTBLOCK(0x40019000, 20K) + VERSTAGE(0x4001E000, 60K) + ROMSTAGE(0x4002D000, 76K) SRAM_END(0x40040000) DRAM_START(0x80000000) |