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authorLijian Zhao <lijian.zhao@intel.com>2018-03-06 03:18:34 +0000
committerPatrick Georgi <pgeorgi@google.com>2018-03-06 08:03:28 +0000
commit345d1e39629b3548e40a82ed6d3d49bdcd5b6b88 (patch)
tree6ad87972b495f74348ea48831704ae171729f31a /src
parent41328938081a38b250bbad69829bbe091abf4e6a (diff)
downloadcoreboot-345d1e39629b3548e40a82ed6d3d49bdcd5b6b88.tar.xz
Revert "mainboard/google/meowth: enable PCH iSCLK"
This reverts commit 2e81f394cffc6f1993a5f004356ed35f6064fe48, as it will have side effect that will make system shutdown failure. System will not enter S5 sleep state, instead a global reset will be generated. Once camera driver ACPI framework ready, isclk programing will be moved into APCI method, in _PS3, isclk will be turned off to save power. BUG=b.72532565 BRANH=master TEST=Apply the changes and flash coreboot, on meowth devices, issue "halt" in OS stage, system can shutdown successfully. Change-Id: If35697911f97c524d9b52bdf4dae5c9ef1cc8618 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25006 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/zoombini/variants/meowth/devicetree.cb3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
index 144b9f2b99..4250121119 100644
--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
@@ -56,9 +56,6 @@ chip soc/intel/cannonlake
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"
- # Enable Pch iSCLK
- register "pch_isclk" = "1"
-
# Touchscreen Digitizer
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST_PLUS,