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authorAndrey Petrov <andrey.petrov@intel.com>2016-11-30 17:39:16 -0800
committerAaron Durbin <adurbin@chromium.org>2016-12-02 16:39:37 +0100
commit3b637531c91d0cb290dcff26584274f41c06ec85 (patch)
treeb12afc65236b99bea416fb1fc8cebae55181d8fa /src
parent91bfa8e7eaf7a91c47a3e86c35ffe2135aa0cd8f (diff)
downloadcoreboot-3b637531c91d0cb290dcff26584274f41c06ec85.tar.xz
soc/intel/apollolake: Enable ACPI PM timer emulation on all CPUs
Currently we enable ACPI PM timer emulation only on BSP. So the timer doesn't work on other cores and that breaks OSes that use it. Also, microcode uses this information to figure out ACPI IO base, and that is used for other features. This patch enables ACPI timer emulation on all the logical CPUs. BUG=chrome-os-partner:60011 TEST=iotools rdmsr x 0x121, x={0..3}, make sure it is set Change-Id: I0d6cb8761c1c25d3a2fcf59a49c1eda9e4ccc70c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17663 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/bootblock/bootblock.c18
-rw-r--r--src/soc/intel/apollolake/cpu.c7
-rw-r--r--src/soc/intel/apollolake/include/soc/pm.h2
-rw-r--r--src/soc/intel/apollolake/pmutil.c18
4 files changed, 28 insertions, 17 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 28a912818f..be10a22736 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -41,22 +41,6 @@ static void tpm_enable(void)
gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs));
}
-static void enable_pm_timer(void)
-{
- /* ACPI PM timer emulation */
- msr_t msr;
- /*
- * The derived frequency is calculated as follows:
- * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer
- * frequency is used.
- */
- msr.hi = (3579545ULL << 32) / CTC_FREQ;
- /* Set PM1 timer IO port and enable*/
- msr.lo = EMULATE_PM_TMR_EN | (ACPI_PMIO_BASE + R_ACPI_PM1_TMR);
- wrmsr(MSR_EMULATE_PM_TMR, msr);
-}
-
static void enable_cmos_upper_bank(void)
{
uint32_t reg = iosf_read(IOSF_RTC_PORT_ID, RTC_CONFIG);
@@ -177,7 +161,7 @@ void bootblock_soc_early_init(void)
if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI))
tpm_enable();
- enable_pm_timer();
+ enable_pm_timer_emulation();
enable_spibar();
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 916d7c5cf4..949736821e 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -28,6 +28,7 @@
#include <reg_script.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
+#include <soc/pm.h>
#include <soc/smm.h>
#include <cpu/intel/turbo.h>
@@ -56,6 +57,12 @@ static void soc_core_init(device_t cpu)
{
/* Set core MSRs */
reg_script_run(core_msr_script);
+ /*
+ * Enable ACPI PM timer emulation, which also lets microcode know
+ * location of ACPI_PMIO_BASE. This also enables other features
+ * implemented in microcode.
+ */
+ enable_pm_timer_emulation();
}
static struct device_operations cpu_dev_ops = {
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index dd9e5265a1..16fc1e4248 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -213,4 +213,6 @@ void global_reset_lock(void);
void pch_log_state(void);
+void enable_pm_timer_emulation(void);
+
#endif
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index c88e5ae8bf..12a1051246 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -21,10 +21,12 @@
#include <arch/io.h>
#include <console/console.h>
#include <cbmem.h>
+#include <cpu/x86/msr.h>
#include <rules.h>
#include <device/pci_def.h>
#include <halt.h>
#include <soc/iomap.h>
+#include <soc/cpu.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <device/device.h>
@@ -551,3 +553,19 @@ void pmc_gpe_init(void)
/* Set the routes in the GPIO communities as well. */
gpio_route_gpe(dw1, dw2, dw3);
}
+
+void enable_pm_timer_emulation(void)
+{
+ /* ACPI PM timer emulation */
+ msr_t msr;
+ /*
+ * The derived frequency is calculated as follows:
+ * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
+ * Back solve the multiplier so the 3.579545MHz ACPI timer
+ * frequency is used.
+ */
+ msr.hi = (3579545ULL << 32) / CTC_FREQ;
+ /* Set PM1 timer IO port and enable*/
+ msr.lo = EMULATE_PM_TMR_EN | (ACPI_PMIO_BASE + R_ACPI_PM1_TMR);
+ wrmsr(MSR_EMULATE_PM_TMR, msr);
+}