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authorSeunghwan Kim <sh_.kim@samsung.com>2018-02-13 16:58:00 +0900
committerMartin Roth <martinroth@google.com>2018-02-15 21:41:51 +0000
commit3f0c7242c9933fba9c6c7d91a96fb75a88aaef15 (patch)
treeb6be3dd299aaf16c65f229945f117d734c0600e6 /src
parentdb9709d67d647329b22eeb6ecc0c5add1276c6ba (diff)
downloadcoreboot-3f0c7242c9933fba9c6c7d91a96fb75a88aaef15.tar.xz
mb/google/poppy/variant/nautilus: Enable and configure DPTF
This change enables DPTF and configures the policy. DPTF parameters were provided by internal power team. BUG=b:67877437 BRANCH=master TEST=emerge-nautilus coreboot Change-Id: I31b31d5282ab38278bc68045ce75fdc6192f1144 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/23731 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/devicetree.cb3
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl65
2 files changed, 66 insertions, 2 deletions
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index be8ab5b55d..9714766055 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -21,6 +21,9 @@ chip soc/intel/skylake
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
+ # Enable DPTF
+ register "dptf_enable" = "1"
+
# Enable S0ix
register "s0ix_enable" = "1"
diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl
index 216b76f157..3fd4a1d748 100644
--- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl
@@ -1,7 +1,8 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2017 Google Inc.
+ * Copyright (C) 2016 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,4 +14,64 @@
* GNU General Public License for more details.
*/
-/* Dummy file until DPTF support is added. */
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 105
+
+#define DPTF_TSR0_SENSOR_ID 1
+#define DPTF_TSR0_SENSOR_NAME "Charger"
+#define DPTF_TSR0_PASSIVE 48
+#define DPTF_TSR0_CRITICAL 90
+#define DPTF_TSR0_TABLET_PASSIVE 44
+#define DPTF_TSR0_TABLET_CRITICAL 90
+
+#define DPTF_TSR1_SENSOR_ID 2
+#define DPTF_TSR1_SENSOR_NAME "DRAM"
+#define DPTF_TSR1_PASSIVE 48
+#define DPTF_TSR1_CRITICAL 90
+#define DPTF_TSR1_TABLET_PASSIVE 44
+#define DPTF_TSR1_TABLET_CRITICAL 90
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+
+ /* Charger Throttle Effect on Charger (TSR0) */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Throttle Effect on DRAM (TSR1) */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 3000, /* PowerLimitMinimum */
+ 7000, /* PowerLimitMaximum */
+ 5000, /* TimeWindowMinimum */
+ 5000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 15000, /* PowerLimitMinimum */
+ 15000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
+
+/* Include DPTF */
+#include <soc/intel/skylake/acpi/dptf/dptf.asl>