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authorArthur Heymans <arthur@aheymans.xyz>2019-11-23 12:55:35 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-03 07:41:40 +0000
commit3fa3bf97e514f046ee9c3d77af4b1a4f8fd07edb (patch)
tree3b7db0ca41bca1fabbe3931654559f0b8ddc5944 /src
parent872fced41dde0b7d168900a61b916682c5cf7b46 (diff)
downloadcoreboot-3fa3bf97e514f046ee9c3d77af4b1a4f8fd07edb.tar.xz
cpu/intel/slot_1: Cache romstage XIP execution
Change-Id: I19fc31a0fe71c5d0c6845a8680e267a0bf5f1a8f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37164 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Keith Hui <buurin@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/slot_1/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index 791997499d..a8d90e8b6f 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -27,6 +27,7 @@ config SLOT_SPECIFIC_OPTIONS # dummy
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
select UNKNOWN_TSC_RATE
+ select SETUP_XIP_CACHE
config DCACHE_RAM_BASE
hex