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authorArthur Heymans <arthur@aheymans.xyz>2017-06-13 14:17:05 +0200
committerMartin Roth <martinroth@google.com>2017-06-16 16:03:14 +0200
commit432ac615d018465e9808be4286c0caf2ca192cf1 (patch)
tree1cfc47666bf6b0673e41a192c9101ff6f12a7130 /src
parent24c3fef31bf08fd8023d7ef89882b271e41cc085 (diff)
downloadcoreboot-432ac615d018465e9808be4286c0caf2ca192cf1.tar.xz
soc/intel/skylake: Don't allow user to change DCACHE base and size
Change-Id: Ic1656311ecc670dc0436995f0ec8199d270da4d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/skylake/Kconfig4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 26f90218d7..fb2d94b974 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -127,11 +127,11 @@ config CPU_ADDR_BITS
default 36
config DCACHE_RAM_BASE
- hex "Base address of cache-as-RAM"
+ hex
default 0xfef00000
config DCACHE_RAM_SIZE
- hex "Length in bytes of cache-as-RAM"
+ hex
default 0x40000
help
The size of the cache-as-ram region required during bootblock