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authorStefan Reinauer <stepan@coresystems.de>2009-04-21 23:01:10 +0000
committerStefan Reinauer <stepan@openbios.org>2009-04-21 23:01:10 +0000
commit4855f56df92477d2082c780055cadc2e96ba0f28 (patch)
tree266a770dd27de6f3e5949aebc710c246920b82ed /src
parent5bba7529d235368530a6e5248710ac053e142f0a (diff)
downloadcoreboot-4855f56df92477d2082c780055cadc2e96ba0f28.tar.xz
add define for Role-Based Error Reporting to PCIe defines (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/include/device/pci_def.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index 1e27647d4b..ba972547ea 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -348,6 +348,7 @@
#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
+#define PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */
#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
#define PCI_EXP_DEVCTL 8 /* Device Control */