AGESA: Use pcidev_on_root()

We have constant CONFIG_CBB==0, replace ill dev_find_slot()
with safe pcidev_on_root();

Change-Id: Ieb2030fa3d77a9f49fc5faf12b92b5f00f49d354
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26482
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

11 files changed, 26 insertions, 25 deletions

diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index ff011e3608..a290eff268 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -46,7 +46,7 @@ static unsigned fx_devs = 0;
 
 static struct device *get_node_pci(u32 nodeid, u32 fn)
 {
-	return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
+	return pcidev_on_root(CONFIG_CDB + nodeid, fn);
 }
 
 static void get_fx_devs(void)
diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c
index 25771d1d2d..98776505ba 100644
--- a/src/northbridge/amd/agesa/family14/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family14/dimmSpd.c
@@ -33,7 +33,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PAR
 {
 	UINT8 spdAddress;
 
-	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2);
 	if (dev == NULL)
 		return AGESA_ERROR;
 
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index b843c799c2..adf7878859 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -43,7 +43,7 @@ static unsigned fx_devs = 0;
 
 static struct device *get_node_pci(u32 nodeid, u32 fn)
 {
-	return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
+	return pcidev_on_root(CONFIG_CDB + nodeid, fn);
 }
 
 static void get_fx_devs(void)
@@ -590,11 +590,12 @@ static void cpu_bus_scan(struct device *dev)
 	int apic_id, cores_found;
 
 	/* There is only one node for fam14, but there may be multiple cores. */
-	cpu = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+	cpu = pcidev_on_root(0x18, 0);
 	if (!cpu)
 		printk(BIOS_ERR, "ERROR: %02x:%02x.0 not found", 0, 0x18);
 
-	cores_found = (pci_read_config32(dev_find_slot(0,PCI_DEVFN(0x18,0x3)), 0xe8) >> 12) & 3;
+	cores_found = (pci_read_config32(pcidev_on_root(0x18, 0x3),
+					0xe8) >> 12) & 3;
 	printk(BIOS_DEBUG, "  AP siblings=%d\n", cores_found);
 
 	for (apic_id = 0; apic_id <= cores_found; apic_id++) {
diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c
index 89aca7d720..8db6095dec 100644
--- a/src/northbridge/amd/agesa/family14/state_machine.c
+++ b/src/northbridge/amd/agesa/family14/state_machine.c
@@ -40,7 +40,7 @@ void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 #ifdef __SIMPLE_DEVICE__
 	pci_devfn_t dev = PCI_DEV(0, 0x18, 2);
 #else
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	struct device *dev = pcidev_on_root(0x18, 2);
 #endif
 	if (boot_cpu()) {
 		u32 mct_cfg_lo = pci_read_config32(dev, 0x118);
diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.c b/src/northbridge/amd/agesa/family15tn/dimmSpd.c
index 528bc4337c..7ca47097b2 100644
--- a/src/northbridge/amd/agesa/family15tn/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.c
@@ -32,7 +32,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PAR
 {
 	UINT8 spdAddress;
 
-	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2);
 	if (dev == NULL)
 		return AGESA_ERROR;
 
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index ae0830c731..f1a2051233 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -99,7 +99,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
 
 static struct device *get_node_pci(u32 nodeid, u32 fn)
 {
-	return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
+	return pcidev_on_root(CONFIG_CDB + nodeid, fn);
 }
 
 static void get_fx_devs(void)
@@ -818,7 +818,7 @@ static void cpu_bus_scan(struct device *dev)
 	int siblings = 0;
 	unsigned int family;
 
-	dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
+	dev_mc = pcidev_on_root(CONFIG_CDB, 0);
 	if (!dev_mc) {
 		printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
 		die("");
@@ -847,7 +847,7 @@ static void cpu_bus_scan(struct device *dev)
 		pbus = dev_mc->bus;
 
 		/* Find the cpu's pci device */
-		cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 0));
+		cdb_dev = pcidev_on_root(devn, 0);
 		if (!cdb_dev) {
 			/* If I am probing things in a weird order
 			 * ensure all of the cpu's pci devices are found.
@@ -857,7 +857,7 @@ static void cpu_bus_scan(struct device *dev)
 				cdb_dev = pci_probe_dev(NULL, pbus,
 							PCI_DEVFN(devn, fn));
 			}
-			cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 0));
+			cdb_dev = pcidev_on_root(devn, 0);
 		} else {
 			/* Ok, We need to set the links for that device.
 			 * otherwise the device under it will not be scanned
@@ -869,11 +869,11 @@ static void cpu_bus_scan(struct device *dev)
 		family = (family >> 20) & 0xFF;
 		if (family == 1) { //f10
 			u32 dword;
-			cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 3));
+			cdb_dev = pcidev_on_root(devn, 3);
 			dword = pci_read_config32(cdb_dev, 0xe8);
 			siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12);
 		} else if (family == 6) {//f15
-			cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 5));
+			cdb_dev = pcidev_on_root(devn, 5);
 			if (cdb_dev && cdb_dev->enabled) {
 				siblings = pci_read_config32(cdb_dev, 0x84);
 				siblings &= 0xFF;
diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c
index 3720c55098..8c453bb7ae 100644
--- a/src/northbridge/amd/agesa/family16kb/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c
@@ -32,7 +32,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PAR
 {
 	UINT8 spdAddress;
 
-	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2);
 	if (dev == NULL)
 		return AGESA_ERROR;
 
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index 03db04235a..cf7e3f86a6 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -98,7 +98,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
 
 static struct device *get_node_pci(u32 nodeid, u32 fn)
 {
-	return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
+	return pcidev_on_root(CONFIG_CDB + nodeid, fn);
 }
 
 static void get_fx_devs(void)
@@ -567,12 +567,12 @@ static void fam16_finalize(void *chip_info)
 {
 	struct device *dev;
 	u32 value;
-	dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
+	dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */
 	pci_write_config32(dev, 0xF8, 0);
 	pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */
 
 	/* disable No Snoop */
-	dev = dev_find_slot(0, PCI_DEVFN(1, 1));
+	dev = pcidev_on_root(1, 1);
 	value = pci_read_config32(dev, 0x60);
 	value &= ~(1 << 11);
 	pci_write_config32(dev, 0x60, value);
@@ -843,7 +843,7 @@ static void cpu_bus_scan(struct device *dev)
 	int siblings = 0;
 	unsigned int family;
 
-	dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
+	dev_mc = pcidev_on_root(CONFIG_CDB, 0);
 	if (!dev_mc) {
 		printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
 		die("");
@@ -872,7 +872,7 @@ static void cpu_bus_scan(struct device *dev)
 		pbus = dev_mc->bus;
 
 		/* Find the cpu's pci device */
-		cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 0));
+		cdb_dev = pcidev_on_root(devn, 0);
 		if (!cdb_dev) {
 			/* If I am probing things in a weird order
 			 * ensure all of the cpu's pci devices are found.
@@ -882,7 +882,7 @@ static void cpu_bus_scan(struct device *dev)
 				cdb_dev = pci_probe_dev(NULL, pbus,
 							PCI_DEVFN(devn, fn));
 			}
-			cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 0));
+			cdb_dev = pcidev_on_root(devn, 0);
 		} else {
 			/* Ok, We need to set the links for that device.
 			 * otherwise the device under it will not be scanned
@@ -894,11 +894,11 @@ static void cpu_bus_scan(struct device *dev)
 		family = (family >> 20) & 0xFF;
 		if (family == 1) { //f10
 			u32 dword;
-			cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 3));
+			cdb_dev = pcidev_on_root(devn, 3);
 			dword = pci_read_config32(cdb_dev, 0xe8);
 			siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12);
 		} else if (family == 7) {//f16
-			cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 5));
+			cdb_dev = pcidev_on_root(devn, 5);
 			if (cdb_dev && cdb_dev->enabled) {
 				siblings = pci_read_config32(cdb_dev, 0x84);
 				siblings &= 0xFF;
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c
index 132a3335af..8d07e6487e 100644
--- a/src/southbridge/amd/agesa/hudson/lpc.c
+++ b/src/southbridge/amd/agesa/hudson/lpc.c
@@ -38,7 +38,7 @@ static void lpc_init(struct device *dev)
 	struct device *sm_dev;
 
 	/* Enable the LPC Controller */
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	sm_dev = pcidev_on_root(0x14, 0);
 	dword = pci_read_config32(sm_dev, 0x64);
 	dword |= 1 << 20;
 	pci_write_config32(sm_dev, 0x64, dword);
diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c
index e98be57575..878f136205 100644
--- a/src/southbridge/amd/agesa/hudson/sd.c
+++ b/src/southbridge/amd/agesa/hudson/sd.c
@@ -25,7 +25,7 @@ static void sd_init(struct device *dev)
 {
 	u32 stepping;
 
-	stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC);
+	stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC);
 
 	struct southbridge_amd_agesa_hudson_config *sd_chip =
 		(struct southbridge_amd_agesa_hudson_config *)(dev->chip_info);
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index 94846514ce..ade7a02376 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -81,7 +81,7 @@ void spi_init(void)
 {
 	struct device *dev;
 
-	dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
+	dev = pcidev_on_root(0x14, 3);
 	spibar = pci_read_config32(dev, 0xA0) & ~0x1F;
 }