diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-13 13:05:48 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-05-22 07:20:14 +0000 |
commit | 4ccb23fe27bc9fa45b6db8a7b4ec519a3c25674b (patch) | |
tree | 9bc7035687e08371ca5216ddaaf219584a131846 /src | |
parent | b7482219e8078ae7ac973b20e5f6aac6d05b7f48 (diff) | |
download | coreboot-4ccb23fe27bc9fa45b6db8a7b4ec519a3c25674b.tar.xz |
sb/intel/fsp_bd82x6x: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: I499414c067b06fa94b53832894e804118f7c3e80
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/azalia.c | 3 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/lpc.c | 20 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/me.c | 14 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 14 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/pch.c | 10 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/pch.h | 2 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/sata.c | 5 | ||||
-rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/watchdog.c | 2 |
8 files changed, 36 insertions, 34 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/azalia.c b/src/southbridge/intel/fsp_bd82x6x/azalia.c index b8cdd9710c..a15279692c 100644 --- a/src/southbridge/intel/fsp_bd82x6x/azalia.c +++ b/src/southbridge/intel/fsp_bd82x6x/azalia.c @@ -334,7 +334,8 @@ static void azalia_init(struct device *dev) pci_write_config8(dev, 0x43, reg8); } -static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void azalia_set_subsystem(struct device *dev, unsigned vendor, + unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index f17a44ff17..431587d426 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -112,9 +112,9 @@ static void pch_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -154,7 +154,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_gpi_routing(device_t dev) +static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -183,7 +183,7 @@ static void pch_gpi_routing(device_t dev) pci_write_config32(dev, GPIO_ROUT, reg32); } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -503,7 +503,7 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -564,18 +564,18 @@ static void pch_lpc_read_resources(device_t dev) } } -static void pch_lpc_enable_resources(device_t dev) +static void pch_lpc_enable_resources(struct device *dev) { pch_decode_init(dev); return pci_dev_enable_resources(dev); } -static void pch_lpc_enable(device_t dev) +static void pch_lpc_enable(struct device *dev) { pch_enable(dev); } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -586,7 +586,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void southbridge_inject_dsdt(device_t dev) +static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -612,7 +612,7 @@ static void southbridge_inject_dsdt(device_t dev) void acpi_fill_fadt(acpi_fadt_t *fadt) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index a4b5f0384d..f3a7824d3a 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -114,7 +114,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) } #ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -542,7 +542,7 @@ void intel_me_finalize_smm(void) #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -609,7 +609,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -639,7 +639,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -686,14 +686,14 @@ static int intel_me_extend_valid(device_t dev) } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); @@ -735,7 +735,7 @@ static void intel_me_init(device_t dev) } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c index fd8b167772..03a9d458ca 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c @@ -115,7 +115,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) } #ifndef __SMM__ -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -521,7 +521,7 @@ void intel_me8_finalize_smm(void) #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -595,7 +595,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -625,7 +625,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -672,14 +672,14 @@ static int intel_me_extend_valid(device_t dev) } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(device_t dev) +static void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { me_bios_path path = intel_me_path(dev); me_bios_payload mbp_data; @@ -737,7 +737,7 @@ static void intel_me_init(device_t dev) } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.c b/src/southbridge/intel/fsp_bd82x6x/pch.c index 3ad45fc585..1613be85b2 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.c +++ b/src/southbridge/intel/fsp_bd82x6x/pch.c @@ -188,9 +188,9 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) } /* Check if any port in set X to X+3 is enabled */ -static int pch_pcie_check_set_enabled(device_t dev) +static int pch_pcie_check_set_enabled(struct device *dev) { - device_t port; + struct device *port; int port_func; int dev_func = PCI_FUNC(dev->path.pci.devfn); @@ -237,7 +237,7 @@ static void pch_pcie_function_swap(u8 old_fn, u8 new_fn) /* Update devicetree with new Root Port function number assignment */ static void pch_pcie_devicetree_update(void) { - device_t dev; + struct device *dev; /* Update the function numbers in the static devicetree */ for (dev = all_devices; dev; dev = dev->next) { @@ -266,7 +266,7 @@ static void pch_pcie_devicetree_update(void) } /* Special handling for PCIe Root Port devices */ -static void pch_pcie_enable(device_t dev) +static void pch_pcie_enable(struct device *dev) { struct southbridge_intel_fsp_bd82x6x_config *config = dev->chip_info; u32 reg32; @@ -373,7 +373,7 @@ static void pch_pcie_enable(device_t dev) } } -void pch_enable(device_t dev) +void pch_enable(struct device *dev) { u32 reg32; diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index 84f21a7f92..5b42271265 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -65,7 +65,7 @@ void intel_pch_finalize_smm(void); int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); -void pch_enable(device_t dev); +void pch_enable(struct device *dev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #if IS_ENABLED(CONFIG_ELOG) void pch_log_state(void); diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c index 6130646629..656dfde6cd 100644 --- a/src/southbridge/intel/fsp_bd82x6x/sata.c +++ b/src/southbridge/intel/fsp_bd82x6x/sata.c @@ -78,11 +78,12 @@ static void sata_init(struct device *dev) } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { } -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void sata_set_subsystem(struct device *dev, unsigned vendor, + unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/fsp_bd82x6x/watchdog.c b/src/southbridge/intel/fsp_bd82x6x/watchdog.c index 74f69b032b..9a867e413a 100644 --- a/src/southbridge/intel/fsp_bd82x6x/watchdog.c +++ b/src/southbridge/intel/fsp_bd82x6x/watchdog.c @@ -28,7 +28,7 @@ // void watchdog_off(void) { - device_t dev; + struct device *dev; unsigned long value, base; /* Turn off the ICH7 watchdog. */ |