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authorBryantOu <Bryant.Ou.Q@gmail.com>2020-04-15 23:17:01 -0700
committerAndrey Petrov <andrey.petrov@gmail.com>2020-04-18 03:39:49 +0000
commit4fc59af03d0d76caa0b8497ea894f360c15c1a39 (patch)
treec97396770f6959848123d4d756a4807dfc963cb7 /src
parentdff56a056c7dadf0d970cfe29f0bc9c1fec69e82 (diff)
downloadcoreboot-4fc59af03d0d76caa0b8497ea894f360c15c1a39.tar.xz
mb/ocp/tiogapass: Pull POST complete pin
Tioga Pass platform use GPIO pin of GPP_B20 for POST complete, BIOS needs to configure this pin for BMC to poll, so it knows when to start to access other components. Tested=Read GPIO status (GPIOAA7) in OpenBMC, the value is 0, the command and result are shown as below, root@bmc-oob:~# cat /tmp/gpionames/FM_BIOS_POST_CMPLT_N/value 0 root@bmc-oob:~# Change-Id: I134f80153461c5acd872587038a2207586b658dd Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/ocp/tiogapass/ramstage.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c
index 8282eb09f4..16b4fd92e3 100644
--- a/src/mainboard/ocp/tiogapass/ramstage.c
+++ b/src/mainboard/ocp/tiogapass/ramstage.c
@@ -13,7 +13,18 @@
* GNU General Public License for more details.
*/
#include <soc/ramstage.h>
+#include <bootstate.h>
+#include <gpio.h>
+#include <soc/lewisburg_pch_gpio_defs.h>
void mainboard_silicon_init_params(FSPS_UPD *params)
{
}
+
+static void pull_post_complete_pin(void *unused)
+{
+ /* Pull Low post complete pin */
+ gpio_output(GPP_B20, 0);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL);