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authorChris Wang <chris.wang@amd.corp-partner.google.com>2018-11-05 12:09:24 +0800
committerMartin Roth <martinroth@google.com>2018-11-09 09:15:11 +0000
commit50c11607a1afaa373d381575c5056e4185a014c4 (patch)
treeea263284ba825dc9ee019655ecedaff0161d3c8d /src
parent2df5abc53bf670786a472c9c315adfc4e988cf2a (diff)
downloadcoreboot-50c11607a1afaa373d381575c5056e4185a014c4.tar.xz
mb/google/kahlee: Tune eDP panel initialization time
1. Add two parameters for panel initialization timing. > lvds_poseq_varybl_to_blon > lvds_poseq_blon_to_varybl 2. The BL_PWM is controlled by APU_EDP_BKLTEN_L/APU_DP_VARY_BL/ EDP_BKLTEN_L, so move APU_EDP_BKLTEN_L to early init stage, and be enabled depends on SKU, thus we can control the delay time by config APU_DP_VARY_BL. BUG=b:118011567 TEST=emerge-grunt coreboot. Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/kahlee/OemCustomize.c26
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/gpio.c6
-rw-r--r--src/soc/amd/stoneyridge/chip.h9
3 files changed, 38 insertions, 3 deletions
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index a0bd8cddbd..12e50724ec 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -16,6 +16,9 @@
#include <chip.h>
#include <amdblocks/agesawrapper.h>
#include <boardid.h>
+#include <gpio.h>
+#include <console/console.h>
+#include <soc/pci_devs.h>
#define DIMMS_PER_CHANNEL 1
#if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH
@@ -75,5 +78,28 @@ void OemPostParams(AMD_POST_PARAMS *PostParams)
void set_board_env_params(GNB_ENV_CONFIGURATION *params)
{
+ const struct soc_amd_stoneyridge_config *cfg;
+ const struct device *dev = dev_find_slot(0, GNB_DEVFN);
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree config\n");
+ return;
+ }
+ cfg = dev->chip_info;
+ if (cfg->lvds_poseq_blon_to_varybl && cfg->lvds_poseq_varybl_to_blon) {
+ /*
+ * GPIO 133 - Backlight enable (active low)
+ * Pass control of the backlight to the video BIOS
+ */
+ gpio_set(GPIO_133, 0);
+ printk(BIOS_INFO, "Change panel init timing\n");
+ params->LvdsPowerOnSeqVaryBlToBlon =
+ cfg->lvds_poseq_varybl_to_blon;
+ params->LvdsPowerOnSeqBlonToVaryBl =
+ cfg->lvds_poseq_blon_to_varybl;
+ printk(BIOS_INFO, "LvdsPowerOnSeqVaryBlToBlon: %dms\n",
+ (params->LvdsPowerOnSeqVaryBlToBlon)*4);
+ printk(BIOS_INFO, "LvdsPowerOnSeqBlonToVaryBl: %dms\n",
+ (params->LvdsPowerOnSeqBlonToVaryBl)*4);
+ }
params->EDPv1_4VSMode = EDP_VS_HIGH_VDIFF_MODE;
}
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index 6095a08af0..f6bc83c4e2 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -77,6 +77,9 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
/* GPIO_132 - CONFIG_STRAP4 */
PAD_GPI(GPIO_132, PULL_NONE),
+ /* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */
+ PAD_GPO(GPIO_133, HIGH),
+
/* GPIO_136 - UART_PCH_RX_DEBUG_TX */
PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
@@ -217,9 +220,6 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
/* GPIO_130 - Unused (TP55) */
PAD_GPI(GPIO_130, PULL_UP),
- /* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */
- PAD_GPO(GPIO_133, HIGH),
-
/* GPIO_135 - BCLK Buffer Enable */
PAD_GPO(GPIO_135, HIGH),
diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h
index 320bef0bdf..92223d1962 100644
--- a/src/soc/amd/stoneyridge/chip.h
+++ b/src/soc/amd/stoneyridge/chip.h
@@ -63,6 +63,15 @@ struct soc_amd_stoneyridge_config {
u8 stapm_percent;
u32 stapm_time_ms;
u32 stapm_power_mw;
+ /*
+ * This specifies the LVDS/eDP power-up sequence time for the delay
+ * between VaryBL and BLON.
+ * 0 - Use the VBIOS default (default). The video BIOS default is 32ms.
+ * n - Values other than zero specify a setting of (4 * n) milliseconds
+ * time delay.
+ */
+ u8 lvds_poseq_varybl_to_blon;
+ u8 lvds_poseq_blon_to_varybl;
};
typedef struct soc_amd_stoneyridge_config config_t;