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authorSubrata Banik <subrata.banik@intel.com>2019-11-28 14:02:10 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-12-03 11:26:49 +0000
commit54daaecacb69194b282484d2c2488c3f5eabc02d (patch)
tree77e48dfce67978635c8e62ad311a63873c17e460 /src
parent73b1bd7992fb33f33c33747fd0919fc495c3d5c4 (diff)
downloadcoreboot-54daaecacb69194b282484d2c2488c3f5eabc02d.tar.xz
mb/google/drallion: Disable GPIO dynamic PM configuration
BUG=b:144002424 TEST=Ensured no TPM time out issue and system can boot to OS Change-Id: I7282e6c2d9627846039638bdc0db3ee7ebba5f12 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb12
-rw-r--r--src/mainboard/google/drallion/variants/drallion/devicetree.cb16
-rw-r--r--src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb12
3 files changed, 21 insertions, 19 deletions
diff --git a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb
index 5f396fe353..11abc87daa 100644
--- a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb
@@ -212,11 +212,13 @@ chip soc/intel/cannonlake
register "gpio_override_pm" = "1"
# GPIO community PM configuration
- register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
- register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
+ # Disable dynamic clock gating; with bits 0-5 set in these registers,
+ # some short interrupt pulses were missed (esp. cr50 irq)
+ register "gpio_pm[COMM_0]" = "0"
+ register "gpio_pm[COMM_1]" = "0"
+ register "gpio_pm[COMM_2]" = "0"
+ register "gpio_pm[COMM_3]" = "0"
+ register "gpio_pm[COMM_4]" = "0"
device cpu_cluster 0 on
device lapic 0 on end
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 4c5cff25a0..2fcf191eae 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -209,15 +209,13 @@ chip soc/intel/cannonlake
register "gpio_override_pm" = "1"
# GPIO community PM configuration
- register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN |
- MISCCFG_GPRTCDLCGEN |
- MISCCFG_GSXSLCGEN |
- MISCCFG_GPDPCGEN |
- MISCCFG_GPDLCGEN"
- register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
+ # Disable dynamic clock gating; with bits 0-5 set in these registers,
+ # some short interrupt pulses were missed (esp. cr50 irq)
+ register "gpio_pm[COMM_0]" = "0"
+ register "gpio_pm[COMM_1]" = "0"
+ register "gpio_pm[COMM_2]" = "0"
+ register "gpio_pm[COMM_3]" = "0"
+ register "gpio_pm[COMM_4]" = "0"
device cpu_cluster 0 on
device lapic 0 on end
diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb
index 8cb1aa3001..c466637918 100644
--- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb
@@ -215,11 +215,13 @@ chip soc/intel/cannonlake
register "gpio_override_pm" = "1"
# GPIO community PM configuration
- register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
- register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
+ # Disable dynamic clock gating; with bits 0-5 set in these registers,
+ # some short interrupt pulses were missed (esp. cr50 irq)
+ register "gpio_pm[COMM_0]" = "0"
+ register "gpio_pm[COMM_1]" = "0"
+ register "gpio_pm[COMM_2]" = "0"
+ register "gpio_pm[COMM_3]" = "0"
+ register "gpio_pm[COMM_4]" = "0"
device cpu_cluster 0 on
device lapic 0 on end