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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2017-09-23 21:39:06 +0200
committerMartin Roth <martinroth@google.com>2017-09-27 16:39:03 +0000
commit5a01d6a152d705ded302e92c4438d8b8dc495465 (patch)
tree139cab8918f8e2503d30c22c26b841d83c31c242 /src
parent7090377a873aaef9715b9ac8e669e9ca1a3b3651 (diff)
downloadcoreboot-5a01d6a152d705ded302e92c4438d8b8dc495465.tar.xz
arch/riscv: trap handler: Print load/store access width in bits
This is easier to read than the raw shift amount that's extracted from load/store instructions. Change-Id: Ia16ab9fbaf55345b654ea65e65267ed900eb29e1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/arch/riscv/trap_handler.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index ca4954f796..4359ed9974 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -245,7 +245,7 @@ void handle_misaligned_load(trapframe *tf) {
insn_t memWidth = (faultingInstruction & widthMask) >> 12;
insn_t destMask = 0xF80;
insn_t destRegister = (faultingInstruction & destMask) >> 7;
- printk(BIOS_DEBUG, "Width: 0x%x\n", memWidth);
+ printk(BIOS_DEBUG, "Width: %d bits\n", (1 << memWidth) * 8);
if (memWidth == 3) {
// load double, handle the issue
void* badAddress = (void*) tf->badvaddr;
@@ -274,7 +274,7 @@ void handle_misaligned_store(trapframe *tf) {
insn_t memWidth = (faultingInstruction & widthMask) >> 12;
insn_t srcMask = 0x1F00000;
insn_t srcRegister = (faultingInstruction & srcMask) >> 20;
- printk(BIOS_DEBUG, "Width: 0x%x\n", memWidth);
+ printk(BIOS_DEBUG, "Width: %d bits\n", (1 << memWidth) * 8);
if (memWidth == 3) {
// store double, handle the issue
void* badAddress = (void*) tf->badvaddr;