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authorTim Wawrzynczak <twawrzynczak@chromium.org>2019-03-21 12:47:21 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-04-09 17:20:59 +0000
commit5ce1698138f59670ab99841ddc3b9e84ba01b571 (patch)
treed3e337fb5151b680cc378da69c5f2d978ae2bd8f /src
parentbaa070a81fb8299ad400636ccb839b651a99a1dc (diff)
downloadcoreboot-5ce1698138f59670ab99841ddc3b9e84ba01b571.tar.xz
mb/google/hatch: Add ACPI support for BT reset functionality
Expose the Bluetooth BT_DISABLE_L signal in Hatch's devicetree, on both USB2 port 5 and 10. BUG=b:123293169 BRANCH=none TEST=compiles, verified kernel is able to find the reset-gpio Change-Id: I6e4d9786e44f12da71533b6740fdd390f3a57e40 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32216 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 2f1120a584..7dd41a2a3a 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -131,6 +131,7 @@ chip soc/intel/cannonlake
chip drivers/usb/acpi
register "desc" = ""Discrete bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)"
device usb 2.4 on end
end
chip drivers/usb/acpi
@@ -146,6 +147,7 @@ chip soc/intel/cannonlake
chip drivers/usb/acpi
register "desc" = ""Integrated CnVi bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)"
device usb 2.9 on end
end
chip drivers/usb/acpi