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authorSubrata Banik <subrata.banik@intel.com>2019-11-14 12:14:39 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-11-15 11:02:37 +0000
commit5d14c76f1ae62d0543614340f4b588adf4f506eb (patch)
treed74a0775bfae5d4a7ae774643795912bec7a354a /src
parent5885ffef326ff41b2bad80e42e1795a2982754b3 (diff)
downloadcoreboot-5d14c76f1ae62d0543614340f4b588adf4f506eb.tar.xz
soc/intel/{icl,tgl}: Rename pch_early_init() to pch_init()
This patch renames pch_early_init() function as per review feedback CB:36550 Change-Id: I9f638e738d1a910b688cc3e51795230b2e542f82 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/icelake/bootblock/bootblock.c2
-rw-r--r--src/soc/intel/icelake/bootblock/pch.c2
-rw-r--r--src/soc/intel/icelake/include/soc/bootblock.h2
-rw-r--r--src/soc/intel/tigerlake/bootblock/bootblock.c2
-rw-r--r--src/soc/intel/tigerlake/bootblock/pch.c2
-rw-r--r--src/soc/intel/tigerlake/include/soc/bootblock.h2
6 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c
index f348c1be6a..fce3cc424c 100644
--- a/src/soc/intel/icelake/bootblock/bootblock.c
+++ b/src/soc/intel/icelake/bootblock/bootblock.c
@@ -40,5 +40,5 @@ void bootblock_soc_early_init(void)
void bootblock_soc_init(void)
{
report_platform_info();
- pch_early_init();
+ pch_init();
}
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c
index b8a404b379..fd2ffd2c88 100644
--- a/src/soc/intel/icelake/bootblock/pch.c
+++ b/src/soc/intel/icelake/bootblock/pch.c
@@ -150,7 +150,7 @@ void pch_early_iorange_init(void)
pch_enable_lpc();
}
-void pch_early_init(void)
+void pch_init(void)
{
/*
* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
diff --git a/src/soc/intel/icelake/include/soc/bootblock.h b/src/soc/intel/icelake/include/soc/bootblock.h
index 4ca2c37288..22e632fc75 100644
--- a/src/soc/intel/icelake/include/soc/bootblock.h
+++ b/src/soc/intel/icelake/include/soc/bootblock.h
@@ -21,7 +21,7 @@ void bootblock_cpu_init(void);
void bootblock_pch_early_init(void);
/* Bootblock post console init programming */
-void pch_early_init(void);
+void pch_init(void);
void pch_early_iorange_init(void);
void report_platform_info(void);
diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c
index f6fe4c4dbd..a4f965947d 100644
--- a/src/soc/intel/tigerlake/bootblock/bootblock.c
+++ b/src/soc/intel/tigerlake/bootblock/bootblock.c
@@ -40,5 +40,5 @@ void bootblock_soc_early_init(void)
void bootblock_soc_init(void)
{
report_platform_info();
- pch_early_init();
+ pch_init();
}
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index c7ccbf8bab..1ef4928fa6 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -156,7 +156,7 @@ void pch_early_iorange_init(void)
pch_enable_lpc();
}
-void pch_early_init(void)
+void pch_init(void)
{
/*
* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
diff --git a/src/soc/intel/tigerlake/include/soc/bootblock.h b/src/soc/intel/tigerlake/include/soc/bootblock.h
index cb7417a107..6dbbfecd02 100644
--- a/src/soc/intel/tigerlake/include/soc/bootblock.h
+++ b/src/soc/intel/tigerlake/include/soc/bootblock.h
@@ -21,7 +21,7 @@ void bootblock_cpu_init(void);
void bootblock_pch_early_init(void);
/* Bootblock post console init programming */
-void pch_early_init(void);
+void pch_init(void);
void pch_early_iorange_init(void);
void report_platform_info(void);