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authorAngel Pons <th3fanbus@gmail.com>2020-03-22 13:00:44 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-26 10:20:09 +0000
commit5fd50b6b198d7e086945ca0255ccc0757b31f748 (patch)
tree7cbbe92d78396d36e8d433dce9a8408cc8eb22af /src
parent098240eb4fd4ef59510d5138538f2a2f7cc5dcdc (diff)
downloadcoreboot-5fd50b6b198d7e086945ca0255ccc0757b31f748.tar.xz
nb/intel/sandybridge: Add and use TC_DTP definition
This register is specific to Ivy Bridge. This changes the binary because the operations get reordered, but it is equivalent. Change-Id: Ibc9127e0fc268466c13f7c5ac8d942543713ca32 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/sandybridge/mchbar_regs.h8
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.c4
2 files changed, 10 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h
index a8ae9c53a9..cf29155f35 100644
--- a/src/northbridge/intel/sandybridge/mchbar_regs.h
+++ b/src/northbridge/intel/sandybridge/mchbar_regs.h
@@ -215,6 +215,10 @@
#define TC_RAP_ch(ch) Cx(0x4004, ch) /* Timings: Regular access */
#define TC_RWP_ch(ch) Cx(0x4008, ch) /* Timings: Read / Write */
#define TC_OTHP_ch(ch) Cx(0x400c, ch) /* Timings: Other parameters */
+
+/** WARNING: Only applies to Ivy Bridge! */
+#define TC_DTP_ch(ch) Cx(0x4014, ch) /** Timings: Debug parameters */
+
#define SCHED_SECOND_CBIT_ch(ch) Cx(0x401c, ch) /* More chicken bits */
#define SCHED_CBIT_ch(ch) Cx(0x4020, ch) /* Chicken bits in scheduler */
#define SC_ROUNDT_LAT_ch(ch) Cx(0x4024, ch) /* Round-trip latency per rank */
@@ -280,6 +284,10 @@
#define TC_RAP 0x4c04 /* Timings: Regular access */
#define TC_RWP 0x4c08 /* Timings: Read / Write */
#define TC_OTHP 0x4c0c /* Timings: Other parameters */
+
+/** WARNING: Only applies to Ivy Bridge! */
+#define TC_DTP 0x4c14 /** Timings: Debug parameters */
+
#define SCHED_SECOND_CBIT 0x4c1c /* More chicken bits */
#define SCHED_CBIT 0x4c20 /* Chicken bits in scheduler */
#define SC_ROUNDT_LAT 0x4c24 /* Round-trip latency per rank */
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index d10b859575..620c57404a 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -216,8 +216,8 @@ void dram_timing_regs(ramctr_timing *ctrl)
printram("OTHP [%x] = %x\n", addr, reg);
MCHBAR32(addr) = reg;
- /* FIXME: This register might as well not exist */
- MCHBAR32(0x4014 + channel * 0x400) = 0;
+ /* FIXME: This register only exists on Ivy Bridge! */
+ MCHBAR32(TC_DTP_ch(channel)) = 0;
MCHBAR32_OR(addr, 0x00020000);