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authorVladimir Serbinenko <phcoder@gmail.com>2016-01-31 14:00:54 +0100
committerMartin Roth <martinroth@google.com>2016-02-09 20:35:40 +0100
commit609bd9445ed1cc76496a9d65ad1d158904d3cf47 (patch)
treeb8ddb349366231d819e828cc8bf785f6da3d7e5d /src
parentbf725b48f730b5996cf1ee7e5ac84ebc0ec78460 (diff)
downloadcoreboot-609bd9445ed1cc76496a9d65ad1d158904d3cf47.tar.xz
ivy: Add a possiblity for mainboard early init.
This is needed for stout EC init. Change-Id: I5c73499c17763229840152a473a2d820802ee2f6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13535 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/apple/macbookair4_2/early_southbridge.c3
-rw-r--r--src/mainboard/gigabyte/ga-b75m-d3h/romstage.c3
-rw-r--r--src/mainboard/gigabyte/ga-b75m-d3v/romstage.c3
-rw-r--r--src/mainboard/google/butterfly/romstage.c3
-rw-r--r--src/mainboard/lenovo/t420s/romstage.c3
-rw-r--r--src/mainboard/lenovo/t430s/romstage.c3
-rw-r--r--src/mainboard/lenovo/t520/romstage.c3
-rw-r--r--src/mainboard/lenovo/t530/romstage.c3
-rw-r--r--src/mainboard/lenovo/x220/romstage.c3
-rw-r--r--src/mainboard/lenovo/x230/romstage.c3
-rw-r--r--src/northbridge/intel/sandybridge/raminit_native.h1
-rw-r--r--src/northbridge/intel/sandybridge/romstage.c3
12 files changed, 34 insertions, 0 deletions
diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c
index 576262d601..67f89db0e3 100644
--- a/src/mainboard/apple/macbookair4_2/early_southbridge.c
+++ b/src/mainboard/apple/macbookair4_2/early_southbridge.c
@@ -52,6 +52,9 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, -1 },
};
+void mainboard_early_init(int s3resume) {
+}
+
void mainboard_get_spd(spd_raw_data *spd)
{
void *spd_file;
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
index 827882015a..ff85ce1795 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -205,3 +205,6 @@ static void dmi_config(void)
DMIBAR32(0x0e2c) = 0x20000000;
}
#endif
+
+void mainboard_early_init(int s3resume) {
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
index b9a8c09b8e..436f82e625 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
@@ -115,3 +115,6 @@ void mainboard_get_spd(spd_raw_data *spd) {
read_spd (&spd[2], 0x52);
read_spd (&spd[3], 0x53);
}
+
+void mainboard_early_init(int s3resume) {
+}
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 6b7562d9e3..40b5e762dc 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -128,3 +128,6 @@ void mainboard_get_spd(spd_raw_data *spd) {
read_spd(&spd[0], 0x50);
read_spd(&spd[2], 0x52);
}
+
+void mainboard_early_init(int s3resume) {
+}
diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c
index 1080e1c2bc..c0204582a7 100644
--- a/src/mainboard/lenovo/t420s/romstage.c
+++ b/src/mainboard/lenovo/t420s/romstage.c
@@ -67,3 +67,6 @@ void mainboard_get_spd(spd_raw_data *spd) {
read_spd(&spd[0], 0x50);
read_spd(&spd[2], 0x51);
}
+
+void mainboard_early_init(int s3resume) {
+}
diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c
index f84cfe3e39..4a99b6d7d6 100644
--- a/src/mainboard/lenovo/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/romstage.c
@@ -67,3 +67,6 @@ void mainboard_get_spd(spd_raw_data *spd) {
read_spd(&spd[0], 0x50);
read_spd(&spd[2], 0x51);
}
+
+void mainboard_early_init(int s3resume) {
+}
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index eb1d0cf995..59bad9a1bf 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -82,3 +82,6 @@ void mainboard_get_spd(spd_raw_data *spd) {
read_spd (&spd[0], 0x50);
read_spd (&spd[2], 0x51);
}
+
+void mainboard_early_init(int s3resume) {
+}
diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index 4003022f56..23f2704391 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -69,3 +69,6 @@ void mainboard_get_spd(spd_raw_data *spd) {
read_spd (&spd[0], 0x50);
read_spd (&spd[2], 0x51);
}
+
+void mainboard_early_init(int s3resume) {
+}
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index ce3f276f89..59b3728665 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -79,3 +79,6 @@ void mainboard_get_spd(spd_raw_data *spd) {
read_spd (&spd[0], 0x50);
read_spd (&spd[2], 0x51);
}
+
+void mainboard_early_init(int s3resume) {
+}
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 316e51dfe4..cf3eb5a76b 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -82,3 +82,6 @@ void mainboard_get_spd(spd_raw_data *spd) {
read_spd (&spd[0], 0x50);
read_spd (&spd[2], 0x51);
}
+
+void mainboard_early_init(int s3resume) {
+}
diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h
index bfdbe8d3eb..b41aa855aa 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.h
+++ b/src/northbridge/intel/sandybridge/raminit_native.h
@@ -24,5 +24,6 @@ void read_spd(spd_raw_data *spd, u8 addr);
void mainboard_get_spd(spd_raw_data *spd);
void rcba_config(void);
void pch_enable_lpc(void);
+void mainboard_early_init(int s3resume);
#endif /* RAMINIT_H */
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 34d759f419..3d05f8e3fa 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -103,6 +103,9 @@ void main(unsigned long bist)
s3resume = southbridge_detect_s3_resume();
post_code(0x38);
+
+ mainboard_early_init(s3resume);
+
/* Enable SPD ROMs and DDR-III DRAM */
enable_smbus();