summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorLee Leahy <leroy.p.leahy@intel.com>2016-05-04 12:50:51 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2016-05-09 17:21:40 +0200
commit614ef408157239db97b08420b93ba051f9428a47 (patch)
tree18747fd2be83fbc16b5f5dbf2290b1e395158076 /src
parentf92a98c56e063b34b83a35ac655ea8127d4b546f (diff)
downloadcoreboot-614ef408157239db97b08420b93ba051f9428a47.tar.xz
soc/intel/quark: Identify the console UART
Pass the UART identifier to CorebootPayloadPkg Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: I9db1c31c3544d56b66f5a79ac8c3acee41788983 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14610 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/quark/Kconfig7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 8485aa3a87..ae25c328c6 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -60,6 +60,13 @@ config TTYS0_LCS
depends on ENABLE_BUILTIN_HSUART1
default 3
+# Console: PCI UART bus 0 << 20, device 20 << 15, function 5 << 12
+# Valid bit, PCI UART in use: 1 << 31
+config UART_PCI_ADDR
+ hex
+ depends on ENABLE_BUILTIN_HSUART1
+ default 0x800a5000
+
#####
# Debug support
# The following options provide debug support for the Quark coreboot