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authorYouness Alaoui <youness.alaoui@puri.sm>2018-05-04 15:34:06 -0400
committerMartin Roth <martinroth@google.com>2018-05-08 02:59:23 +0000
commit71616784077cd5a712dcb8768cea3464c3de04ec (patch)
treef616bcb092d13f66ac436e9ffa6d37ddd626e712 /src
parent1f64b01bbe0007f0364d23715ff0aef0a1eec336 (diff)
downloadcoreboot-71616784077cd5a712dcb8768cea3464c3de04ec.tar.xz
intel/broadwell: Add option to enable/disable the PCIe AER capability
The Advanced Error Reporting capability was hardcoded in the PCIe extended capability list, but it might not always be possible. The Librem 13v1 does not seem to have working AER and this option was needed and tested on the Librem 13v1. Without it, the linux console gets spammed with AER errrors. Change-Id: If2e0ec42c93f1fee927eacdf0099004cf9302fbe Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/25326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/broadwell/Kconfig4
-rw-r--r--src/soc/intel/broadwell/pcie.c8
2 files changed, 10 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index cfab4895b9..5d8d602121 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -47,6 +47,10 @@ config PCIEXP_ASPM
bool
default y
+config PCIEXP_AER
+ bool
+ default y
+
config PCIEXP_COMMON_CLOCK
bool
default y
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index db948596a5..724f26328f 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -555,8 +555,12 @@ static void pch_pcie_early(struct device *dev)
pci_update_config8(dev, 0xf5, 0x0f, 0);
/* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
- pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
- (1 << 29) | 0x10001);
+ if (IS_ENABLED(CONFIG_PCIEXP_AER))
+ pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
+ (1 << 29) | 0x10001);
+ else
+ pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
+ (1 << 29));
/* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE))