diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2012-05-17 17:21:27 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-05-29 11:29:24 +0200 |
| commit | 71695d8a28f6081dc63a06203f68a5365aa9af97 (patch) | |
| tree | 4fac5f77ff01f5e3c89db051ff8fe18a8eefca5f /src | |
| parent | 984f9540c0ac2fe25d6057134b86aeca4a091803 (diff) | |
| download | coreboot-71695d8a28f6081dc63a06203f68a5365aa9af97.tar.xz | |
Fix full reset for Ivy Bridge platforms
Experiments have shown that writing plain value of 6 at byte io
address of 0xcf9 causes the systems to reset and reboot reliably.
Change-Id: Ie900e4b4014cded868647372b027918b7ff72578
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1050
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/reset.c | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c index 29b69ff43a..5324142621 100644 --- a/src/southbridge/intel/bd82x6x/reset.c +++ b/src/southbridge/intel/bd82x6x/reset.c @@ -26,16 +26,7 @@ void soft_reset(void) outb(0x04, 0xcf9); } -#if 0 void hard_reset(void) { - /* Try rebooting through port 0xcf9. */ - outb((1 << 2) | (1 << 1), 0xcf9); -} -#endif - -void hard_reset(void) -{ - outb(0x02, 0xcf9); outb(0x06, 0xcf9); } |