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authorIonela Voinescu <ionela.voinescu@imgtec.com>2015-05-26 12:20:19 +0100
committerMartin Roth <martinroth@google.com>2015-12-21 02:06:12 +0100
commit721f2998a5d4143f7d609e79255d570b43d804a4 (patch)
tree38323779ba458202158c2d3e9655045d79834970 /src
parent6b95406ff3d44679d2e0139236c134655b12b927 (diff)
downloadcoreboot-721f2998a5d4143f7d609e79255d570b43d804a4.tar.xz
imgtec/pistachio: DDR2, DDR3: DLL reset set
Bit 8 of the MR register is automatically set by the PHY during memory initilization but having it set in the register leads to a more clear understanding. Tested on Pistachio bring up board; DDR2 and DDR3 are initialized properly. Change-Id: Ie6953e2a96ba2961521b372d280f362ee1c52b94 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12764 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/imgtec/pistachio/ddr2_init.c2
-rw-r--r--src/soc/imgtec/pistachio/ddr3_init.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c
index 322d241164..9549537261 100644
--- a/src/soc/imgtec/pistachio/ddr2_init.c
+++ b/src/soc/imgtec/pistachio/ddr2_init.c
@@ -112,7 +112,7 @@ int init_ddr2(void)
* 15:13 RSVD RSVD
* 31:16 Reserved
*/
- write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000A62 | (BL8 ? 0x1 : 0x0));
+ write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000B62 | (BL8 ? 0x1 : 0x0));
/* MR1 : EMR Register
* Generate to use with PHY and PCTL
* 0 DE DLL Enable 0 Disable 1
diff --git a/src/soc/imgtec/pistachio/ddr3_init.c b/src/soc/imgtec/pistachio/ddr3_init.c
index e77a5cde9c..5cb36a07b8 100644
--- a/src/soc/imgtec/pistachio/ddr3_init.c
+++ b/src/soc/imgtec/pistachio/ddr3_init.c
@@ -119,7 +119,7 @@ int init_ddr3(void)
* 15:13 RSVD RSVD
* 31:16 Reserved
*/
- write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001420);
+ write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001520);
/* MR1 : DDR3 mode register 1
* Generate to use with PHY and PCTL
* 0 DE DLL Enable 0 Disable 1